7286 - Verilog Compiler Simulator (VCS) simulation: Error-[URMI] Unresolved modules
Description:
In VCS, an error can occur when simulating designs with some foundational IPs.
Solution:
This is due to the 'include lines in the Verilog files used for the IP/s. Thus, VCS cannot resolve these modules.
See the following steps to be able to run your VCS simulation (example design using PMI instantiation of memory):
1. Combine all your source files in a single .f file.
2. See the following example:
3. This will allow us to directly reference VCS to the correct file.
4. See the following VCS call with the .f file:
vcs -R -debug_access+all -timescale=1ps/1ps -sverilog +define+DEBUG=0 +define+SIMULATE +notimingchecks +libext+.v +define+functional +v2k \
+incdir+/tools/dist/lattice/RADIANT/2023_1p.43.3/Linux/cae_library/simulation/verilog/lfmxo5/ \
+incdir+/tools/dist/lattice/RADIANT/2023_1p.43.3/Linux/cae_library/simulation/verilog/uaplatform/ \
+incdir+/tools/dist/lattice/RADIANT/2023_1p.43.3/Linux/ip/pmi/ \
+incdir+/*location of test.f*/ \
-y /tools/dist/lattice/RADIANT/2023_1p.43.3/Linux/cae_library/simulation/verilog/lfmxo5/ \
-y /tools/dist/lattice/RADIANT/2023_1p.43.3/Linux/cae_library/simulation/verilog/uaplatform/ \
-y /tools/dist/lattice/RADIANT/2023_1p.43.3/Linux/ip/pmi/ \
-f /*location of test.f*/test.f \
This should apply to other designs using IP/s if they use 'include lines to refer to other files.
Related Articles
7776 - Radiant / Third-Party Simulation Tools: How to simulate a PCIE IP in Synopsys VCS or Cadence Xcelium?
Description: This example details the simulation flow for a PCIe server IP targeting the MachXO5 device using manual Radiant library references in VCS. or Xcelium The process includes configuring environment variables, generating the IP from the ...7728 - VCS Simulation: Error-[XMRE] Cross-module reference resolution error
Description: This error is found when trying to simulate using Lattice libraries on Synopsys VCS. Solution: This is caused by a missing GSR instantiation in the user testbench. GSR is needed because all Lattice hard blocks are connected to GSR. ...7774 - Radiant / Third-Party Simulation Tools: How to simulate a PLL IP thru manual library referencing in Synopsys VCS or Cadence Xcelium?
Description: This example outlines a fallback simulation method for a Phase-Locked Loop IP on the MachXO5 device using Synopsys VCS or Cadence Xcelium. It involves manually referencing the Radiant device library using +incdir/-incdir (VCS/Xcelium) ...7269 - Modelsim for Diamond 3.13: "Error: (vsim-3043) Unresolved reference to I2C_WAKE"
Description: When simulating EFB in Lattice Diamond 3.13 & earlier version Modelsim OEM, due to the default enabled optimization setting of Modelsim, the error below will occur: "Error: (vsim-3043) Unresolved reference to I2C_WAKE" Solution: This is ...7777 - Radiant / Third-Party Simulation Tools: General Guidance on Library Compilation Methods and IP Generation
Description: This FAQ complements Application Note FPGA-AN-02084 by offering practical guidance for using Synopsys VCS and Cadence Xcelium in Lattice FPGA simulations. It expands on the original note with real-world examples involving Lattice IPs and ...