Verilog Compiler Simulator (VCS) simulation: Error-[URMI] Unresolved modules
Description:
In VCS, an error can occur when simulating designs with some foundational IPs.
Solution:
This is due to the 'include lines in the Verilog files used for the IP/s. Thus, VCS cannot resolve these modules.
See the following steps to be able to run your VCS simulation (example design using PMI instantiation of memory):
1. Combine all your source files in a single .f file.
2. See the following example: