Synthesis Inquiry / Failure
6814 - Lattice Radiant: Why do i encounter a synthesis error from my iCE40 Ultra Plus Design, shown below:# ** Error: (vsim-3033) Instantiation of 'SB_HFOSC' failed. The design unit was not found.# ** Error: (vsim-3033) Instantiation of 'SB_IO_OD' failed. The design unit was not found.
Description: Users will encounter a synthesis error when utilizing SB_* primitives on Radiant tool. Solution: SB_* primitives (Example: are SB_HFOSC) are only used in iCECube2 SW. The primitives have their equivalents in Radiant (Example: HFOSC), So ...
7226 - Synplify Pro on Diamond version 3.13 and older: evaluation of mixed real-integer expressions is wrong
Description: On Diamond 3.13 and older, when using Synplify Pro as the Synthesis Tool, the evaluation of mixed real-integer expressions is wrong. Solution: For such expressions, please include ".0" until this can be fixed in a future version of the ...
7207 - ispLever Clasic 2.1 and below: How to avoid optimization of unconnected pins in a schematic entry on ispLever Classic?
To avoid optimization on unconnected pins in a schematic entry, click on the input/output symbol output net and edit the net attribute "preserve" or "keep" and set it to Y.
7205 - Lattice Diamond/Radiant: How do I preserve the components of my design for both Radiant and Diamond? How do I prevent unwanted optimization by the tool?
The only way to preserve (even names) those net/signals into your netlist is through the utilization of the Synthesis Attributes. Unfortunately, there is no additional feature for preventing optimization. You can use the following: 1) syn_keep on a ...
7200 - Synthesis Error for SystemVerilog design: "Error: No definition for function <>"
Description: In synthesizing a SystemVerilog design, this error will come up if there are entities that are not synthesizable. Solution: There is no planned fix for this issue since these are for non-synthesizable entities. There are certain entities ...
6785 - Radiant / Synplify Pro: Why does Postsyn reject the user's pre-synthesis constraints on an FDC file when Reveal Inserter is included in the project?
Description: The issue is caused by some differences in the behavior of the Verific and Synplify language parsers related to the handling of the escape characters in the instance name. Solution: This is not yet fixed by Synplify Pro and no timeline ...
6780 - Lattice Radiant: How to solve the postsyn error - instantiating unknown module <module_name>?</module_name>
Description: Synthesis provides an error whenever it encounters a module from that does not exist within the design. In some case, this is encountered if a blackbox for an secured module is not present within the design location. Solution: If there ...
6758 - Diamond / Synplify Pro: Can the user ignore the "Unsupported property <parameter_name> found - ignoring" warnings of specific parameters when synthesizing using Synplify Pro?
Yes, these warnings are safe to ignore. These warnings occur because, for any Verilog parameter or localparam, Synplify Pro will pass it with a value into EDIF as part of the original design info. Since such property cannot be recognized by ...
6757 - Synplify Pro: Why is the design failing synthesis when user included Reveal which is previously passing synthesis without Reveal?
The insertion of Reveal uses Verific's parser instead of Synplify Pro's parser. Due to the difference in parser behavior, there are rare cases that synthesis will pass without Reveal using Synplify Pro's parser, but fail once Reveal is inserted while ...
7136 - Diamond: What is the usage of the synthesis strategy setting "Frequency" of Synplify Pro/Lattice LSE?
The frequency setting only applies to clocks with undefined frequencies through the SDC constraints create_clock and create_generated_clock constraints. As observed in the screenshots, Synplify Pro accepts SDC constraints through the Synthesis ...
7306 - Radiant 2023.2: Why does Synthesis fail when using SynplifyPro on Ubuntu 22.04?
Description: Radiant 2023.2 and lower versions are not officially supported on Ubuntu 22.04. We highly suggest using the official supported Linux platform mentioned in each software version release notes since those operating systems are Software QA ...
6163 - Lattice Diamond LSE: When trying to instantiate the gddr_7:1 ip core, why do I get a Multiple Driver Error?
Description: When IP is synthesized, Tool propagates a Warning and Error shown WARNING - Net direction has following drivers : instance Inst_bw_align ERROR - c:/lscc/gddrtest666/gddr_clarity/gddr71/gddr71.v(1284): net direction is constantly driven ...
7119 - Diamond version 3.12 SP1 and older on Windows 11: ERROR - logical block ... is unexpanded
Description: In Diamond version 3.12 SP1 and older, "ERROR - logical block ... is unexpanded" can be encountered in Synthesis when using Windows 11. Solution: There is no planned fix for this issue. This is due to Windows 11 support for Diamond 3.12 ...
6160 - Diamond: WARNING - Unsupported property ASYNC_REG found
Description: The Async_Reg is an unsupported property in the software which is why this placing attribute is ignored. What we could suggest is that you can add an HGROUP attribute in the RTL code. For example, a design that contains double ...
6142 - Lattice Diamond: Why LSE and Synplify Pro has different RTL View implementation?
LSE and Synplify Pro use different parsers to parse the design files. LSE uses Verific parser, a third-party tool for Lattice, and the same is used by Netlist Analyzer to infer the RTL view. Synplify Pro uses its own parser, and HDL Analyst uses this ...
6605 - Synthesis Warning: Removing unused instance VDB-5034
Description: In Synthesis, the user can encounter the warning removing unused instance VDB-5034. Solution: This usually means the instance is floating and not used. To address this warning, users can modify their RTL code or apply a synthesis ...
6602 - Synthesis warning: Skipping pad insertion on <pin> due to black_box_pad_pin attribute.
Description: In synthesis, the user may encounter this warning if the synthesis tool skips the IO pad insertion when a 'black_box_pad_pin' attribute is found on the port. Solution: Users may refer to the following from Radiant Help for ...
6599 - Radiant: What is the cause of the synthesis error stating: Synthesis ERROR - *: instantiating unknown module '<instance_name>'?
Description: This is typically happens if a design that uses mixed language (Verilog/SystemVerilog + VHDL) has mismatch port widths. Solution: To avoid this error, make sure that both Verilog/SystemVerilog and VHDL modules has the same port widths ...
7097 - Radiant: Why the registers not initialized properly during netlist simulation and hardware validation?
Description: Similar description and explanation with FAQ-7241. Solution: When using VHDL for your design please check if you are using Synplify Pro as synthesizing tool. Lattice Synthesis Engine (LSE) currently have issues with VHDL. Using Synplify ...
6120 - Lattice Diamond/DCSC Primtive IP: 2019990 ERROR - Port SEL does not exist.
Description: When user used the DCSC Verilog instantiation code from TN02200 and run the design flow compilation, user may observed error in Synthesis run as below. 2019990 ERROR - Port SEL does not exist Solution: To workaround this error message, ...
6042 - iCECube2: @E::Signal 011 error in m_generic.. how to deal with it?
Current workaround for this error is to replace the DFF instantiation with one that used a custom module functionally the same as the official black box DFF.
6038 - Lattice LSE: Why does LSE fail when VHDL files are compiled into a library directory name other than "work"?
To workaround this issue, it is required that the top-level VHDL file must be compiled into a library called 'work'. The Lower-level VHDL files can be compiled into other library naming.
7042 - Lattice Diamond: Why does my design with Lattice Sentry i2c filter core failed compilation with "Synthesis exit by 9" and "Done: error code 9" error message?
Description: Users utilize i2c filter encounter Synthesis Exit by 9 when synthesizing their design on Diamond Solution: This is due to wrong FPGA tool selection on the IP parameter. Make sure you choose the correct software tool in the IP core ...
6525 - Lattice Diamond: Why do i encounter a WARNING from my design relating to Diamond's Security feature?
Description: When user design is compiled (Synthesis --> Bitstream) a Warning shown below is encountered WARNING -Security project file open Error! Security feature is turned OFF! Solution: The warning is valid and is just providing message that the ...
7028 - Lattice Radiant/Diamond: How does Synplify Pro infer a Single Clock or Dual Clock FIFO?
The FIFO primitive is not inferable by our synthesis tool, in this case, if you implement FIFO logic it will always use LUTS/REGISTERS/FLOPS for its utilization. Users must have to instantiate the FIFO16K primitive for it to be utilized. In this ...
6491 - Lattice iCECube2: Why do i encounter a synthesis error referring to multiple top level candidates when compiling my design?
Description: Error is encountered during synthesis as shown below @N:There are multiple top-level candidates. @E: CH100 : | Encountered multiple top-level candidates in design; compilation stopped. Solution: This error occurs if tool detects multiple ...
6473 - Diamond 3.12: Why is it that error was detected when using VHDL 2008 with Reveal?
Description: After synthesis, specific error produced by the tool is stated as below: C:/lscc/diamond/3.12/cae_library/vhdl_packages/../../ispfpga/vhdl_packages/vh2008/ieee/syn_misc_2008.vhd(22): ERROR: 'attributes' is not compiled in library ...
5929 - Lattice Diamond: How do we tell the software to reduce the DSP block utilization and use LUTs instead?
Lattice Synthesis Engine (LSE) has the ability to reduce the total DSP block utilization using these steps: Go to Project > Active Implementation > Select Synthesis Tool Select "Lattice LSE" and click OK. Go to Project > Active Strategy > LSE ...
6994 - Lattice Radiant: How do I use the RGB pins on iCE40UltraPlus as GPIO?
The SB_IO_OD primitive is only available for the iCECube2 SW, you will have to use BB_OD as this is the equivalent primitive for the opendrain buffer in Radiant. Note that for Radiant, BB_OD is automatically mapped in the netlist/design whenever you ...
6469 - Diamond: Does HDL Parameter in Implementation option support boolean value?
For the LSE synthesis tool, the HDL Parameter in the Implementation option does not accept literal boolean value (true/false). It only allows its equivalent value, which is 0 for false and 1 for true. Example code: condition_a : boolean := false HDL ...
5914 - Lattice Diamond: Why do i get an error message when I add my encrypted RTL file with `include?
Description: When utilizing the `include with RTL files that are encrypted, the synthesis tool generates an error. Solution: Verific in Diamond does not recognize the encrypted file inside a ‘include this an SW limitation and not possible for them to ...