Lattice Radiant/Diamond: How does Synplify Pro infer a Single Clock or Dual Clock FIFO?

Lattice Radiant/Diamond: How does Synplify Pro infer a Single Clock or Dual Clock FIFO?

The FIFO primitive is not inferable by our synthesis tool, in this case, if you implement FIFO logic it will always use LUTS/REGISTERS/FLOPS for its utilization. Users must have to instantiate the FIFO16K primitive for it to be utilized. In this case, we suggest creating an IP and checking the generated RTL file (.v file) as an example of how the primitive is utilized for either a single clock or dual clock fifo.