6599 - Radiant: What is the cause of the synthesis error stating: Synthesis ERROR - *: instantiating unknown module '<instance_name>'?

6599 - Radiant: What is the cause of the synthesis error stating: Synthesis ERROR - *: instantiating unknown module '<instance_name>'?

Description:
This is typically happens if a design that uses mixed language (Verilog/SystemVerilog + VHDL) has mismatch port widths.

Solution:
To avoid this error, make sure that both Verilog/SystemVerilog and VHDL modules has the same port widths declaration.
Example with error:
In Verilog/SystemVerilog Top module:
.i_as0_haddr  ('0),
In VHDL sub-module:
i_as0_haddr : in  std_logic_vector(31 downto 0);

Example without error:
In Verilog/SystemVerilog Top module:
.i_as0_haddr  (32'h00000000),
In VHDL sub-module:
i_as0_haddr : in  std_logic_vector(31 downto 0);