Diamond: What is the usage of the synthesis strategy setting "Frequency" of Synplify Pro/Lattice LSE?
The frequency setting only applies to clocks with undefined frequencies through the SDC constraints create_clock and create_generated_clock constraints.
As observed in the screenshots, Synplify Pro accepts SDC constraints through the Synthesis Constraints file (.SDC). This will affect how synthesis is performed. Without a synthesis constraint, it will use the Strategy setting Frequency (MHz) for all the undefined clocks during the synthesis process.
As an example, see an undefined clock through port clk_in in the synthesis constraints.
See that in the Process Reports > Synplify Pro > Top > Clock Summary, it is using the 200 MHz specified on the strategy setting: