7200 - Synthesis Error for SystemVerilog design: "Error: No definition for function <>"

7200 - Synthesis Error for SystemVerilog design: "Error: No definition for function <>"

Description:
In synthesizing a SystemVerilog design, this error will come up if there are entities that are not synthesizable.

Solution:
There is no planned fix for this issue since these are for non-synthesizable entities.

There are certain entities like string and .len that are not synthesizable. This is usually used in testbenches, not in the design itself.