Lattice iCECube2: Why do i encounter a synthesis error referring to multiple top level candidates when compiling my design?<div><br></div>

Description:

Error is encountered during synthesis as shown below

@N:There are multiple top-level candidates. @E: CH100 : | Encountered multiple top-level candidates in design; compilation stopped.

Solution:

This error occurs if tool detects multiple independent files (unrelated design files) in your project. Having independent files in one project causes compilation error during synthesis, VHDL entity should be instantiated under a Verilog top wrapper or Verilog entity module in a VHDL top wrapper to get it synthesized.

Related Articles
Lattice Diamond: Why do i encounter a WARNING from my design relating to Diamond's Security feature? <div><br></div>
Description: When user design is compiled (Synthesis --> Bitstream) a Warning shown below is encountered WARNING -Security project file open Error! Security feature is turned OFF! Solution: The warning is valid and is just providing message that the ...
Lattice Radiant: Why do i encounter a synthesis error from my iCE40 Ultra Plus Design, shown below: # ** Error: (vsim-3033) Instantiation of 'SB_HFOSC' failed. The design unit was not found. # ** Error: (vsim-3033) Instantiation of 'SB_IO_OD' failed. The design unit was not found.
Description: Users will encounter a synthesis error when utilizing SB_* primitives on Radiant tool. Solution: SB_* primitives (Example: are SB_HFOSC) are only used in iCECube2 SW. The primitives have their equivalents in Radiant (Example: HFOSC), So ...
Lattice Radiant: Why do i encountering an error from duplicate modules when running synthesis?
Description: User is encountering the below error when design is synthesized. ERROR - Duplicate modules named <> between libraries Solution: There are two possible solutions for this error as shown below: (1) Synplify Pro searches for the work.<VHDL ...
<div>Lattice Diamond: How do i set multiple verilog include directories on my design?</div><div><br></div>
You can add multiple directories in the "Verilog Include Search Path" in Design implementation, you can define them as (Example): C:/Users/cmeala/Desktop/CASES/Include Case/Path1;C:/Users/cmeala/Desktop/CASES/Include Case/Path2 then try using ...
Lattice Diamond: Why does my design encounter a MAP error shown below when running the design flow? ERROR - <signal_name> matches no clock nets in the design.
Description: This is encountered if the signal is being defined (for example in constraint file) and that signal is optimized (or the net does not actually exist in the design) by the synthesis tool, To fix the error add in the following attribute to ...

Lattice iCECube2: Why do i encounter a synthesis error referring to multiple top level candidates when compiling my design?<div><br></div>

Lattice iCECube2: Why do i encounter a synthesis error referring to multiple top level candidates when compiling my design?<div><br></div>

Related Articles

Lattice Diamond: Why do i encounter a WARNING from my design relating to Diamond's Security feature?&nbsp;<div><br></div>

Lattice Radiant: Why do i encounter a synthesis error from my iCE40 Ultra Plus Design, shown below: # ** Error: (vsim-3033) Instantiation of 'SB_HFOSC' failed. The design unit was not found. # ** Error: (vsim-3033) Instantiation of 'SB_IO_OD' failed. The design unit was not found.

Lattice Radiant: Why do i encountering an error from duplicate modules when running synthesis?

<div>Lattice Diamond: How do i set multiple verilog include directories on my design?</div><div><br></div>

Lattice Diamond: Why does my design encounter a MAP error shown below when running the design flow? ERROR - <signal_name> matches no clock nets in the design.

Lattice Diamond: Why do i encounter a WARNING from my design relating to Diamond's Security feature? <div><br></div>

Lattice Radiant: Why do i encounter a synthesis error from my iCE40 Ultra Plus Design, shown below: # Error: (vsim-3033) Instantiation of 'SB_HFOSC' failed. The design unit was not found. # Error: (vsim-3033) Instantiation of 'SB_IO_OD' failed. The design unit was not found.