Lattice Diamond: Why does my design encounter a MAP error shown below when running the design flow?
ERROR - <signal_name> matches no clock nets in the design.
Description:
This is encountered if the signal is being defined (for example in constraint file) and that signal is optimized (or the net does not actually exist in the design) by the synthesis tool, To fix the error add in the following attribute to the signal.
Solution:
To work around this issue, assuming the net is actually existing from the RTL design, use a synthesis attribute shown below to prevent the tool fromoptimizing the net from both Synthesis and Map perspective.
/*synthesis syn_keep=1 NOMERGE = "ON" */;