Yes, these warnings are safe to ignore.
These warnings occur because, for any Verilog parameter or localparam, Synplify Pro will pass it with a value into EDIF as part of the original design info. Since such property cannot be recognized by back-engines, warnings are generated but can be ignored. By back-engines, we mean the back-end processes of Translate Design, where EDIF is translated to NGD.
As a sanity check, even though there are "Unsupported property... - ignoring" warnings related to specific parameters, the parameter values will still be reflected on the netlist. User can confirm this on the Technology View of Synplify Pro by right-clicking and checking the value of the specific parameter.