Description:
When user used the DCSC Verilog instantiation code from TN02200 and run the design flow compilation, user may observed error in Synthesis run as below.
2019990 ERROR - Port SEL does not exist
Solution:
To workaround this error message, user required to split the SEL in the instance into SEL0 and SEL1.
Sample Verilog source code is provided below:
module top (
input CLK0, CLK1 ,SEL0, SEL1, MODESEL,
output DCSOUT); /*synthesis syn_black_box*/
parameter DCSMODE = "POS";
DCSC DCSInst0 (
.CLK0 (CLK0 ),
.CLK1 (CLK1 ),
.SEL0 (SEL0 ),
.SEL1 (SEL1 ),
.MODESEL (MODESEL),
.DCSOUT (DCSOUT));
Note: Remember to not use DCSC as module name as it was reserve for the IP name.
For more information, user may refer to the Lattice Diamond Help page and search for DCSC.
<Diamond installation path>/<Diamond version>/docs/webhelp/eng/index.htm