Synplify Pro: Why is the design failing synthesis when user included Reveal which is previously passing synthesis without Reveal?
The insertion of Reveal uses Verific's parser instead of Synplify Pro's parser. Due to the difference in parser behavior, there are rare cases that synthesis will pass without Reveal using Synplify Pro's parser, but fail once Reveal is inserted while using the Verific parser.
As an example, Verific requires that any field for a record with data type std_logic_vector have a defined range. Synplify Pro would accept the undefined range for std_logic_vector and would not show any error.