2354 - All FPGA: How do I add delay to a net in my design?

Description:

To add or control a net's delay manually is useful in some cases to improve hold time or adjust the skew between two nets. In order to add delay to a net, one or more buffers need to be added to the net. You will also need to add attributes and preferences to ensure the buffers do not get removed during the Synthesis and MAP processes.

Here is the sample code:

in Verilog:

module add_del(din,dout);
input din;
output dout;

wire buf1 /* synthesis syn_keep=1 nomerge=""*/;
wire buf2 /* synthesis syn_keep=1 nomerge=""*/;

BUFBA del1(.Z(buf1), .A(din))/* synthesis loc = "R3C3D" */;
BUFBA del2(.Z(buf2), .A(buf1))/* synthesis loc = "R3C4D" */;

assign dout = buf2;

endmodule

module BUFBA (Z, A);

output Z ;
input A ;

endmodule // BUFFER

in VHDL:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity add_del is
port (din : in std_logic;
      dout : out std_logic);
end entity add_del;

architecture RTL of add_del is
component BUFBA is
port (
   A    : in std_logic;
   Z    : out std_logic
);
end component;

signal buf1 : std_logic;
signal buf2 : std_logic;

attribute syn_keep : boolean;
attribute syn_keep of buf1, buf2 : signal is true;
attribute nomerge : string;
attribute nomerge of buf1, buf2 : signal is "";

attribute loc : string;
attribute loc of del1 : label is "R3C3D";
attribute loc of del2 : label is "R3C4D";

begin

del1 : BUFBA port map ( A => din, Z => buf1);
del2 : BUFBA port map ( A => buf1, Z => buf2);

dout <= buf2;

end architecture RTL;

In the code, the module "BUFBA" is the Lattice primitive for a buffer.

The "syn_keep" attribute is the synthesis attribute to keep the specified net intact during optimization and synthesis.

The "nomerge" preference is the Lattice preference to prevent the net from being absorbed into a logic block during MAP.

The loc preference is used to lock the location of the buffers.

In the above example, two buffers are added. The number of buffers used depends on how much delay needs to be added. Locking the location of the buffers allows some measure of routing delay control. The closer the locations of the two buffers are, the smaller the routing delay. The real delay can be found in the Place and Route TRACE Report, see the example below:

      Data path din to dout:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---    0.508         C4.PAD to         C4.PADDI din
ROUTE         1      0.911       C4.PADDI to         R3C3D.C0 din_c
CTOF_DEL    ---      0.179       R3C3D.C0 to         R3C3D.F0 SLICE_1
ROUTE         1      0.409       R3C3D.F0 to         R3C4D.D0 buf1
CTOF_DEL    ---      0.179       R3C4D.D0 to         R3C4D.F0 SLICE_0
ROUTE         1      0.753       R3C4D.F0 to         C3.PADDO buf2
DOPAD_DEL   ---      2.359       C3.PADDO to           C3.PAD dout
                    --------
                     5.298   (60.9% logic, 39.1% route), 4 logic levels.

The SLICE_1 and SLICE_0 in the above Resource information contain the two buffers (i.e., buf1 and buf2). And their corresponding LUT and routing delay are added as in the above Delay information.

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2354 - All FPGA: How do I add delay to a net in my design?

2354 - All FPGA: How do I add delay to a net in my design?

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Lattice Diamond: Why does my design encounter a MAP error shown below when running the design flow? ERROR - <signal_name> matches no clock nets in the design.