Timing Closure Inquiry / Failure
7277 - Lattice Radiant / PLL: What compilation process or stage does the software automatically define the create_generated_clock constraints of the PLL clock outputs? Can the user use the generated clocks on other constraints define in the pre-synthesis stage (e.g. set_clock_groups, etc.)?
Any clock output of the PLL has an automatically create_generated_clock constraint defined in the post-synthesis stage. Thus, user can use the generated clocks on their constraints as long as they are using post-synthesis constraints. If the user ...
6422 - All Nexus / Radiant version 2023.1 or earlier: Are there any guidelines when changing the speed grades for Place & Route Design and Place & Route Timing Analysis on the strategy settings?
It is not recommended to change the default speed grade settings for both the Place & Route (PAR) Design and Place & Route Timing Analysis. DEFAULT VALUES: The default values (especially for HOLD) are for worst case timing calculations. For PAR ...
7274 - How can the user set a false path on my pre-synthesis constraint files (SDC/FDC) between the PLL clock outputs if these are generated in the post-synthesis stage?
To set this as false_path in pre-synthesis, user need to define the create_generated_clock on the SDC/FDC file as well. Just make sure that the create_generated_clock constraint at the pre-synthesis stage captures all of the properties of the PLL ...
7263 - Lattice Diamond: Are the hold window analysis violations observed on the Timing Analysis View valid timing violations? Do users need to make sure that these are passing even though they are not blocking bitstream generation?
Even though PAR timing did not show any timing violations, users/designers must check the Timing Analysis View for hold window violations. Hold Window analysis is only for boundary paths, i.e. paths involving input or output ports specified with an ...
7260 - Diamond: How to insert/use the IO register to improve timing?
There are three ways to do this: 1. IO Registering strategy setting: Depending on the IO pin's direction that user wants to have connected to the IO register, they can set it to Input, Output, or Both. Please refer to the Diamond Help for more ...
6851 - Diamond: Why is the HOLD_OFFSET on the timing report a negative value when using the INPUT_DELAY option on the INPUT_SETUP preference?
Based on the preferences section of Diamond Help, this is a normal/expected behavior of the timing engine and is seen on the timing reports. INPUT_DELAY is independent of frequency/period and would take the negative of the hold value as the ...
6304 - Lattice Diamond: By using the hard D-PHY of Crosslink, why does the FREQUENCY PORT declared in the constraint file changed to FREQUENCY NET in the timing analyzer which then generates a warning message?
For hardened blocks like hardened DPHY, the timing analyzer cannot read the hardened blocks once constraining them. As a recommendation, the designer should constrain the other clocks that are actually used to clock soft logic, like the byte clocks ...
6828 - Diamond: How does Timing Analysis use the CLKOFFSET value of the INPUT_SETUP preference?
Consider an example report with INPUT_SETUP preferences, one with a 0.5 X CLKOFFSET and another one with -0.5 X CLKOFFSET. The calculation should be the following: Externally, user is using a positive-edge triggered flop and internally the tool is ...
6827 - Diamond: How to add falling clock to INPUT_SETUP constraint/preference in Diamond?
1. Try using Synplify Pro as the synthesis tool and migrate your LDC file to an SDC file (please put the correct names of the clock, ports, nets, and pins as these might change when changing synthesis tool.) 2. Use INPUT_SETUP preference. This has ...
7239 - Diamond / FDP-Link Receiver IP version 1.4.0: How can user resolve the timing violations on paths within the FDP-Link Receiver IP related to the reset pin of clkdivg instance and the pll lock of the bw_align instance of the IP?
Paths to the reset pin of clkdivg instance are asynchronous paths. To solve the timing violation, user can add this BLOCK preference/constraint: BLOCK PATH TO ASIC "*fpd_link_rx_inst/fpd_link_rx_inst/clkdivg_inst0" PIN "RST" ; Important note: Please ...
6826 - Radiant: What type of clocks do the Clock Port column of the I/O Timing Analysis Report refer to?
For I/O timing analysis, the "Clock Port" column/field could refer to the following depending on the destination clock: 1. Internal oscillator clock: If the destination clock is directly from the internal oscillator, or if the destination clock is ...
6265 - Lattice Diamond: Does Diamond timing analysis account for package flight time?
The timing data are measured on the IP boundary; that is, for pin-to-pin delays, that is the timing from the input port of the IP to the output port of the IP. This takes into account the load that the IP sees based on its connections. In the case of ...
7228 - Radiant: Why is the speed grade showing that it is using a timing model at 1.0V and not lowest specified supply voltage which is 0.95V?
The 1.0 V specified on the speed grade 8_High-Performance_1.0V is just the name of the speed grade. By default, the voltage used for the setup analysis corner is 0.95 V. You can see this on the Device Constraints Editor (DCE) --> Global Tab --> ...
6256 - Diamond: What is the difference of HOLD and HOLD_WINDOW?
Diamond Timing Analysis View does Setup and Hold Analysis along with hold-window calculation. The setup calculation is done based on the user speed grade. The hold calculation is done based on the minimum speed grade and the hold_window calculation ...
6806 - All Nexus / Radiant: Why can't users see reset signals on the timing analysis reports even without setting the set_false_path constraints?
Resets are not timed or cannot be checked on the timing analysis reports if they are using Global/Set Reset (GSR) component. GSR will be used if the following are set: 1. GSR is instantiated on the RTL and set to the reset signal. 2. GSR-related ...
7199 - Lattice Radiant: How do I achieve 100% timing coverage?
To achieve 100% timing coverage, you must define the following constraints: 1) create_clock constraint on all your clock ports 2) create_generate_clocks on all nets/pins/ports 3) set_input_delay and set_output_delay on your input and output ports. ...
6789 - How can prohibiting the usage of dedicated clock resources help solve hold timing violations?
Primary/Secondary routing resources have less delay and low skew compared to local/general routing. One of the reasons for having a hold violation is that the data path is reaching the latch/end/capture flop faster than the clock path. When ...
7188 - Lattice Radiant version 2022.1 and 2023.1: Why does the Radiant Timing Report indicate an unconstrained path for path with applied constraint such as <i>set_input_delay</i>?
Description: When a user defines a set_input_delay on a port, the timing report will indicate that the port/paths related to the port are unconstrained. Solution: This is a known issue. This is scheduled to be fixed on Fix in Radiant 2023.2.
7187 - Lattice Radiant: How do i constraint a path with false path at Pre-Synthesis?
It is not recommended to constraint from pin to pin in pre-synthesis path thus set_false_path may not be applicable. Instead, use post-synthesis path to do the set_false_path constraint. (use PDC)
7185 - What would happen on the timing analysis if user set a negative value on the set_input_delay constraint?
User can either set the negative value on the -max option or on the -min option: 1. Setting a negative value for the -max option of the set_input_delay: When user set a value of the set_input_delay for the -max option, this applies to the setup ...
6787 - Radiant: Is it recommended to check the initial timing report generated by Synplify Pro under the SRR file?
Customers should not be using the timing report generated by Synplify Pro. There is a warning on the Synplify Pro timing report to refer to the FPGA vendor place and route report. See the warning below: Please use the timing report generated by ...
7167 - Lattice Radiant: What are the Timing constraints for PMI_FIFO_DC using EBR IMPLIMENTATION?
Here are the constraints to be used: set_max_delay -from [get_pins -hierarchical */*wp_sync1_r*.ff_inst/Q] -to [get_pins -hierarchical */*wp_sync2_r*.ff_inst/DF] 2 set_max_delay -from [get_pins -hierarchical */*rp_sync1_r*.ff_inst/Q] -to [get_pins ...
6771 - Radiant 2023.2 SP1 or earlier: How can user handle clock-domain-crossing (CDC) paths timing violations between rvlclk and another clock of the design (clk)?
These timing violations only occur if we use soft JTAG for Reveal. To handle this, user can use a set_false_path constraint between the clocks as these paths are invalid.
7165 - Lattice Radiant: Do I need to constrain the LPDDR4 Output ports?
The training logic sets the delay value of OUTDELAYA primitive during training. The Radiant Timing Engine cannot set the delay value, so users should not add set_output_delay constrain on the Output Port.
7420 - Radiant: Why is the result of my timing different on the PAR report compared with the TWR report?
The result from .PAR and from .TWR is expected to be different. For Radiant 2023.2, multi-corner timing analysis is implemented, the idea is for: A. 2023.2 1) PAR Timing Analysis (.PAR) - The Timing model used is the model with "WORST" case at ...
6737 - Radiant: Does Radiant perform static timing analysis (STA) on reset pins/signals?
Radiant performs static timing analysis (STA) on reset pin/signals that are using Local Set/Reset (LSR). To use LSR, user need to make sure that the GSR-related strategy settings are False/OFF (Force GSR on Synthesis and Infer GSR on MAP). User also ...
7403 - Radiant: How to further check the paths/connections in the design that are not covered by constraints?
To look into unconstrained connections from the design, use -dump_uncovered on the Place & Route Timing Analysis Strategy Settings, As shown below: The -dump_uncovered command creates a log file in the design directory named UncoveredConn.log this ...
6734 - Radiant: "WARNING - The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets."
In Radiant, this warning occurs because the user have some create_clock constraints defined on nets. If the clocks have connected top-level ports or driver pins, the user must consider moving the constraint objects of the create_clock constraints to ...
6188 - Radiant 3.0 and below: What is the difference in timing analysis between Radiant 2.2 versus 3.0?
As verified with the SW team, there was some issue in the previous builds which was fixed in the later builds. GBB numbers have been updated in R3.0. There were some changes in the cell data from R2.2 to R3.0 We highly suggest asking customers to use ...
7134 - Diamond: Is there a section or a tool where user can find the metastable CDC paths and if they are properly handled or not with FIFO or synchronizer FFs?
In the timing report, there is a Clock Domains Analysis (CDC) section. It doesn't report if the CDC is handled properly through synchronizers or FIFOs. This should be the designer's responsibility, as we currently do not have a DRC that checks for ...
7128 - Diamond version 3.13 or earlier: Is there a way to specify jitter values to each PLL clock output individually in Diamond?
Upon checking, there are only two ways to consider jitter on the clocks. Either through SYSTEM_JITTER preference or the CLOCK_JITTER option on the FREQUENCY preference: 1. SYSTEM_JITTER: This applies same jitter to all of the clocks of the design. 2. ...
7121 - Lattice Radiant: How do I constrain my Soft DPHY Data lanes?
You may refer to Section 5.22.2 (DDR Input Setup and Hold Time Constraints) of CrossLink-NX High-Speed I/O Interface Technical Note (FPGA-TN-02097-1.8) while referencing the values found in Section 3.17 (External Switching Characteristics). For ...
7113 - Lattice Radiant: What is a possible reason for an LPDDR4 Memory Controller timing violation for Nexus Devices?
The timing issue can be due to the CPU. The LPDDR4 MC instantiates a small Risc-V CPU which implements the LPDDR4 training routes. This CPU runs on pclk_i which can be at a different frequency with aclk_i. The maximum frequency for pclk_i, when the ...
7108 - Lattice Radiant: Why am I getting setup timing violations while using pmi_fifo_dc IP with HARD_IP implementation?
To fix the CDC path violations, please use the following constraints: set_max_delay -from [get_pins -hierarchical */*.FIFO16K_MODE_inst/FULL] -to [get_pins -hierarchical \{*/*.full_r.*_inst/LSR}] 4 set_max_delay -from [get_pins -hierarchical ...
7081 - Radiant: How can user perform Timing Analysis using a different speed grade other than the speed grade of the selected device (or the PAR speed grade)?
To perform Timing Analysis on different speed grades independent of the PAR speed grade, user can change the Timing Analysis speed grade in 3 ways: 1. Change the strategy setting for PAR Timing Analysis speed grades to a different speed grade than ...
7075 - Lattice Radiant/Diamond: Do I need to constrain internal paths found on Hard Blocks (Lattice primitives)?
Timing within hard blocks are already optimized. Paths utilized in the primitive are already consistent hence Ideally there is no need to have them (the paths inside) constrained separately. Users would just need to connect the input/output ports to ...
7069 - Radiant version 2023.1 or newer: Are there priority rules when multiple timing exception constraints are applied on a specific timing path?
Kindly refer below to the exception priority: 1. set_false_path 2. set_max_delay or set_min_delay 3. set_multicycle_path A couple of notes: 1. set_max_skew applies to the timing path together with exception constraint that takes priority. 2. ...
6547 - All FPGA: Does Radiant has "PAR ADJ" similar to the Diamond?
Description: No mention of PAR adjust in Radiant Help unlike in Diamond that is helpful in timing closure. Solution: The user can use “clock uncertainty” within constraint editor (starting from pre-synth). It will act as "PAR ADJ" and somewhat ...
7060 - Radiant: When to use a create_clock or create_generated_clock constraint? What are the consequences if a create_clock constraint is used instead of a create_generated_clock constraint?
Use create_clock constraints when the clock is coming from an input port. Use create_generated_clock constraints when the clock is generated from a module or circuit inside the FPGA design through multiplication or division of a base clock. The ...
7051 - Radiant: Why is the NBR Summary seems to be showing different values compared to the PAR Timing Report in terms of number of timing violations?
There is an info and note on the Place & Route report that mentions that NBR calculations are different from the calculations on the Place & Route Timing Report.
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