Lattice Radiant/Diamond: Do I need to constrain internal paths found on Hard Blocks (Lattice primitives)?

• Related Articles

• Lattice Radiant: Do I need to constrain the LPDDR4 Output ports?

  The training logic sets the delay value of OUTDELAYA primitive during training. The Radiant Timing Engine cannot set the delay value, so users should not add set_output_delay constrain on the Output Port.

• Lattice Diamond and Radiant Programmer: Does Lattice Programmer software and driver support FT4232HQ?

  Both Lattice Diamond and Radiant Programmer are not support FT4232HQ.

• 7480 - Lattice Radiant: Why are there missing timing paths analyzed on R3.0 when it was compared with R3.1 and later?

  Description: When users try to compare timing analysis paths from R3.1 and later with R3.0, there are timing violations/timing paths found in R3.1 and later that cannot be found in R3.0. Solution: This is a known issue on Software version R3.0 The ...

• 1365 - Lattice Diamond: When using revision control in Diamond software, how to archive project files with minimum hard disk space usage?

  Lattice Diamond: There are options to archive only the necessary project files in Diamond: Open "Options" dialog (Menu "Tools"-> "Options...") and uncheck "Archive all files under the Project directory when archiving Project" in ...

• Lattice Diamond: By using the hard D-PHY of Crosslink, why does the FREQUENCY PORT declared in the constraint file changed to FREQUENCY NET in the timing analyzer which then generates a warning message?

  For hardened blocks like hardened DPHY, the timing analyzer cannot read the hardened blocks once constraining them. As a recommendation, the designer should constrain the other clocks that are actually used to clock soft logic, like the byte clocks ...