7239 - Diamond / FDP-Link Receiver IP version 1.4.0: How can user resolve the timing violations on paths within the FDP-Link Receiver IP related to the reset pin of clkdivg instance and the pll lock of the bw_align instance of the IP? 

Paths to the reset pin of clkdivg instance are asynchronous paths.

To solve the timing violation, user can add this BLOCK preference/constraint:

BLOCK PATH TO ASIC "*fpd_link_rx_inst/fpd_link_rx_inst/clkdivg_inst0" PIN "RST" ;

Important note: Please put the design's hierarchy on the above constraint for it to be accepted by the tool.

Paths to the pll lock of the bw align instance are also asynchronous paths.

To solve the timing violation, user can add this BLOCK constraint:

BLOCK PATH TO CELL "*fpd_link_rx_inst/fpd_link_rx_inst/bw_align_inst0/pll_lock_r0*" ;

Important note: Please put the design's hierarchy on the above constraint for it to be accepted by the tool.

7239 - Diamond / FDP-Link Receiver IP version 1.4.0: How can user resolve the timing violations on paths within the FDP-Link Receiver IP related to the reset pin of clkdivg instance and the pll lock of the bw_align instance of the IP?&nbsp;