Radiant Timing Analyzer: Why is the PLL Lock Signal not included in the Timing Analyzer?
The PLL lock signal is generally asynchronous with respect to the user's system clock domains. This means that the signal does not have a predictable relationship with the system clock, making it challenging to model accurately in the software timing model. As a result, the Radiant Timing Analyzer does not include this signal in its timing analysis.
The PLL lock signal can be used in simulation to observe the sequence of events and how it affects other signals of interest, such as reset release or enabling logic. This can help you understand the behavior of your design under different conditions.