The PLL lock signal is generally asynchronous with respect to the user's system clock domains. This means that the signal does not have a predictable relationship with the system clock, making it challenging to model accurately in the software timing ...
Description: When opening Reveal Analyzer, signals will appear to reset or hang. The Reveal version in Radiant being used includes the following: 2023.2 SP1, 2024.1, 2024.1 SP1. Solution: This is a known issue and is planned to be fully fixed in ...
One common cause for this issue for iCE40 Ultraplus Breakout boards is failing to use the HW-USBN-2B cable as shown on page 43 of the tutorial. Here's a direct link to the document: http://www.latticesemi.com/view_document?document_id=52758 Unlike ...
In order to ran through Timing simulation for iCECube2 Devices, You would need the following Libraries: 1) sb_ice_ipenc_modelsim.v [Optional: Add this if Hardened IPs are present in your design, Example: SPI, i2C] 2) sb_ice_lc.v 3) sb_ice_syn.v 4) ...
Description: See the following steps to set the TCK Low Width Delay to >10x: 1. Program a device with the Reveal core 2. Create a .rva file 3. Edit the .rva file in a text editor. Change the following line: 4. Save the .rva file in your text editor ...