7650 - Radiant 2023.2 SP1 to Radiant 2024.1 SP1 Reveal Analyzer: signal appears to hang or reset

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• Lattice Radiant and Diamond: How do i resolve core0 error when Running reveal analyzer? How to resolve Error "Core0 incorrect pattern readout" while running Reveal Analyzer?

  Description: When running the reveal analyzer a "Core0 incorrect pattern readout" error is encountered causing the tool to not generate its desired waveforms. Solution: This can be resolved by making sure that you have the following: 1) JTAG TCK is ...

• Radiant and Diamond: How do you view or print a waveform with ModelSim/Questa using the VCD file generated by Reveal Analyzer?

  Description: The VCD (Value change dump) file is an ASCII file defined by IEEE 1364. It can be generated by a Verilog command or system function which can be used as the stimulus to the testbench and record variations of waveform. Here are the steps ...

• Reveal Analyzer on iCE40 Ultraplus Breakout Board: What is the common cause of core0 incorrect pattern readout?

  One common cause for this issue for iCE40 Ultraplus Breakout boards is failing to use the HW-USBN-2B cable as shown on page 43 of the tutorial. Here's a direct link to the document: http://www.latticesemi.com/view_document?document_id=52758 Unlike ...

• Radiant: Does Radiant perform static timing analysis (STA) on reset pins/signals?

  Radiant performs static timing analysis (STA) on reset pin/signals that are using Local Set/Reset (LSR). To use LSR, user need to make sure that the GSR-related strategy settings are False/OFF (Force GSR on Synthesis and Infer GSR on MAP). User also ...

• Lattice Nexus devices using Reveal: no output from LVDS IP

  Description: While debugging your Radiant design using Reveal, users may observe that there is no output from their LVDS IP. Solution: When Reveal is inserted in Nexus devices, on certain designs, the GSR net gets assigned to a reset signal that may ...