6771 - Radiant 2023.2 SP1 or earlier: How can user handle clock-domain-crossing (CDC) paths timing violations between rvlclk and another clock of the design (clk)?

6771 - Radiant 2023.2 SP1 or earlier: How can user handle clock-domain-crossing (CDC) paths timing violations between rvlclk and another clock of the design (clk)?

These timing violations only occur if we use soft JTAG for Reveal. To handle this, user can use a set_false_path constraint between the clocks as these paths are invalid.