7480 - Lattice Radiant: Why are there missing timing paths analyzed on R3.0 when it was compared with R3.1 and later?
Description:
When users try to compare timing analysis paths from R3.1 and later with R3.0, there are timing violations/timing paths found in R3.1 and later that cannot be found in R3.0.
Solution:
This is a known issue on Software version R3.0
The Issue is generated by a SW Bug/behavior when a Parent Clock and a Child clock is defined within a set_clock_group constraints. A Child clock is the clock that is generated by a Parent clock. For Example, A PLL module generates 2 clocks (CLKOP and CLKOS), while its input clock is CLKIN, CLKOP and CLKOS is considered to be the Child clock of the Parent Clock CLKIN. Note that it is also possible for a generated clock to be the Parent clock of another clock.
For Example:
When looking into the design below, It can be seen that the reason why the clk0/1 are the only one affected is that , sysclock is the PARENT CLOCK of clk0 and clk1. clk0 and clk1 are CHILD Clocks of the mentioned clock, since sysclock , clk0, and clk1 are in the set_clock_group , it caused an issue on the CHILD CLOCKS where the CHILD CLOCKS generated a false path relationship to itself. The sysclock is the same clock that generates the clk0 and clk1 making it as their PARENT CLOCK as shown below: