Lattice Radiant: What are the Timing constraints for PMI_FIFO_DC using EBR IMPLIMENTATION?
Here are the constraints to be used:
set_max_delay -from [get_pins -hierarchical */*wp_sync1_r*.ff_inst/Q] -to [get_pins -hierarchical */*wp_sync2_r*.ff_inst/DF] 2
set_max_delay -from [get_pins -hierarchical */*rp_sync1_r*.ff_inst/Q] -to [get_pins -hierarchical */*rp_sync2_r*.ff_inst/DF] 2
set_multicycle_path -from [get_pins -hierarchical */*rd_grey_sync_r*.ff_inst/Q] 2
set_multicycle_path -from [get_pins -hierarchical */*wr_grey_sync_r*.ff_inst/Q] 2
set_false_path -from [get_pins -hierarchical */*rd_addr_arith_r*.ff_inst/Q] -to [get_pins -hierarchical */*rp_sync1_r*.ff_inst/DF]
set_false_path -from [get_pins -hierarchical */*wr_addr_arith_r*.ff_inst/Q] -to [get_pins -hierarchical */*wp_sync1_r*.ff_inst/DF]
set_multicycle_path -hold -end -from [get_pins -hierarchical */*rd_grey_sync_r*.ff_inst/Q] 1
set_multicycle_path -hold -end -from [get_pins -hierarchical */*wr_grey_sync_r*.ff_inst/Q] 1
The path is from the rd_addr_r/rd_addr_arith_r and wr_addr_r/wr_addr_arith_r to flop synchronizers (rp_sync1_r and wp_sync1_r) which are the first flops in CDC sync path. There are two separate clocks for read and write and they can happen simultaneously, they are asynchronous. If you look into the netlist of the implementation, The flops are clocked directly from the ports which are two different sources, there is no clear indication that there is a relationship between WrClock and RdClock, they are asynchronous. Since these are synchronizers, it is not required to meet timing from the rd_addr_r/wr_addr_r to the first flop, since they are used in handling metastability.