The Lattice Static Timing Analyzer Trace analyzes all clock domain transfers in which it can relate the source and destination clock domains. This may not always be desired. User may utilize their own synchronizer to handle the transfer between the clock domains. In this case, trace should not analyze the clock domain transfer. This can be done in three ways.

1. BLOCK INTERCLOCKDOMAIN PATHS
   This preference will block all clock domain transfers in the design. If all of the clock domain transfers in the design are handled by the logic within the design then this can be used. Be careful with this preference since it will stop TRACE from analyzing all clock domain transfers.
2. BLOCK PATH FROM CLKNET "src_clk" TO CLKNET "dst_clk"
   This preference will block all clock domain transfers from src_clk to dst_clk. This covers all of the transfers between these two domains. All other clock domain transfers will be reported and timed by TRACE.
3. BLOCK FROM CELL "myff1*" TO CELL "myff2*"
   This preference will block the clock domain transfer from myff1* to myff2*. This is a very specific path and is useful if user have several different types of clock domain transfers between two domains. For example, a design may contain an asynchronous FIFO and a FF-to-FF domain transfer between the same domains. The asynchronous FIFO transfer can be safely blocked, but the FF-to-FF transfer needs to be timed.