How can the user set a false path on my pre-synthesis constraint files (SDC/FDC) between the PLL clock outputs if these are generated in the post-synthesis stage?

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• Lattice Radiant / PLL: What compilation process or stage does the software automatically define the create_generated_clock constraints of the PLL clock outputs? Can the user use the generated clocks on other constraints define in the pre-synthesis stage (e.g. set_clock_groups, etc.)?

  Any clock output of the PLL has an automatically create_generated_clock constraint defined in the post-synthesis stage. Thus, user can use the generated clocks on their constraints as long as they are using post-synthesis constraints. If the user ...

• Lattice Radiant: How do i constraint a path with false path at Pre-Synthesis?

  It is not recommended to constraint from pin to pin in pre-synthesis path thus set_false_path may not be applicable. Instead, use post-synthesis path to do the set_false_path constraint. (use PDC)

• All FPGA: Why does PLL outputs' constraints does not propagate from ldc/fdc/sdc to Synthesis using both SynplifyPro & LSE?

  Description: Lattice Diamond software does not use any pre-synthesis constraint file (SDC/LDC/FDC). Solution: There is a workaround to compensate for the limitation. Once the user has created any pre-synthesis constraint file, synthesize the design ...

• Lattice Radiant: Why does the constraint coverage did not improve after using set_false_path constraint?

  By Default, set_false_paths does not improve constraint coverage, however For Radiant 2023.1 or later, the user can use the Timing Command Line Option "-false_covers" to add in the false paths to the timing coverage. This can be applied on the ...

• Radiant: When to use a create_clock or create_generated_clock constraint? What are the consequences if a create_clock constraint is used instead of a create_generated_clock constraint?

  Use create_clock constraints when the clock is coming from an input port. Use create_generated_clock constraints when the clock is generated from a module or circuit inside the FPGA design through multiplication or division of a base clock. The ...