You may refer to Section 5.22.2 (DDR Input Setup and Hold Time Constraints) of CrossLink-NX High-Speed I/O Interface Technical Note (FPGA-TN-02097-1.8) while referencing the values found in Section 3.17 (External Switching Characteristics).
For Example, let us say we have a 200MHz clock and at 9 Performance grade.
For Receive Interface:
Set_input_delay -clock <clock_name> -max <delay> [get_ports <port_name>]
Calculation: tsu_GDDRX4_MP = 0.2 x UI
; UI = ½ (Clock Period) = ½ (5 ns) = 2.5ns
= 0.2 x 2.5 ns = 0.5 ns
Set_input_delay -clock <clock_name> -min <delay> [get_ports <port_name>]\
Calculation: tsu_GDDRX4_MP = 0.133 ns
Resulting Constraints:
Set_input_delay -clock {dsi_rx_clk} -max 0.5 [get_ports {dsi_rx_d_p[*]} ]
Set_input_delay -clock {dsi_rx_clk} -min 0.133 [get_ports {dsi_rx_d_p[*]} ]