Lattice Radiant / PLL: What compilation process or stage does the software automatically define the create_generated_clock constraints of the PLL clock outputs? Can the user use the generated clocks on other constraints define in the pre-synthesis stage (e.g. set_clock_groups, etc.)?

Lattice Radiant / PLL: What compilation process or stage does the software automatically define the create_generated_clock constraints of the PLL clock outputs? Can the user use the generated clocks on other constraints define in the pre-synthesis stage (e.g. set_clock_groups, etc.)?

Any clock output of the PLL has an automatically create_generated_clock constraint defined in the post-synthesis stage. Thus, user can use the generated clocks on their constraints as long as they are using post-synthesis constraints.

If the user wants to have generated clock constraints on pre-synthesis stage, user can override its definitions through constraints on an SDC or FDC file.


Once user have defined it in the pre-synthesis stage, user will be able to use the generated clock on other constraints like a false path constraint as seen in the example below:

The constraints used in the FDC file are the following:
# PLL reference clock
create_clock -name {clk} -period 10 [get_ports clk] 
# PLL CLKOP
create_generated_clock -name {clk_w} -source [get_ports clk] -multiply_by 2 [get_nets clk_w]
# False path constraint on CDC
set_false_path -from [get_clocks clk] -to [get_clocks clk_w]


As a way to check if the FDC/SDC constraints are accepted, user should be able to see them with the Pre-Synthesis label on the All Constraints View of the Post-Synthesis Timing Constraints Editor.