7128 - Diamond version 3.13 or earlier: Is there a way to specify jitter values to each PLL clock output individually in Diamond?
Upon checking, there are only two ways to consider jitter on the clocks. Either through SYSTEM_JITTER preference or the CLOCK_JITTER option on the FREQUENCY preference:
1. SYSTEM_JITTER: This applies same jitter to all of the clocks of the design.
2. CLOCK_JITTER: This applies jitter only to incoming clocks from clock ports of the PLL.
Unfortunately, users do not have any constraint/preference or options to specify jitter values for each of the clock outputs of the PLL.
There is a workaround users can do for this. User can overconstrain the PLL output clocks to account for the jitter.
As an example:
Let's say user have a PLL with a PLL clock output of 100 MHz and 50 MHz. This will be the setting in the IP GUI.