Radiant: When to use a create_clock or create_generated_clock constraint? What are the consequences if a create_clock constraint is used instead of a create_generated_clock constraint?
Use create_clock constraints when the clock is coming from an input port.
Use create_generated_clock constraints when the clock is generated from a module or circuit inside the FPGA design through multiplication or division of a base clock. The module or circuit here can be any clock generators such as an IP or primitive (PLL, CLKDIV, etc.) or user defined logic that multiplies and divides clock.
If a create_clock constraint is used instead of a create_generated_clock, the report would be missing delays on the clock path (the clock insertion and generation delays). This would lead to incorrect slacks related to the specific clock and possibly a false timing closure of the design.
Clock path when using create_generated_clock constraint: See that the path starts with the pad going into the clock generator circuit, in this case a PLL, and out of the PLL going to the FF.
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