PCIe x4
PCIe: Procedures to run CertusPro-NX PCIe simulation using Cadence Xcelium simulator.
1. During PCIE_X4 IP generation in Lattice Radiant tool, follow below GUI settings. i) Simulation Reduce Timeout = 1 ii) Register Interface Type = LMMI iii) Non-DMA mode: Data Interface Type = TLP DMA Enabled mode: Data Interface Type = AXI_MM 2. ...
1329 - Is it possible to implement two full X4 PCIe endpoints in one device? I am interested in a non transparent bridge application...
It is possible to implement several x4 PCIe endpoints in a single Lattice device. Here are some possible solutions. LatticeECP3 devices LFE3-70 and 95 can support 2 x4 PCIe endpoints LFE3-150 can support up to 4 x4 PCIe endpoints LatticeECP2M devices ...
6900 - PCIe for Nexus FPGAs: How can the PCIe configuration space settings in the RTL of the demo be interpreted?
Description: To understand the RTL formatting of the PCIe configuration space in the Nexus' PCIe demos, please refer to the following details. Figure 1 illustrates the initialization of the PCIe configuration space in the Nexus' demo.
7158 - CertusPro-NX/PCI Express: Why does PCIe Gen3x1 and Gen3x4 simulation takes longer time to link-up?
Solution: The RTL fix will be release on the new IP version (pciex4 ver. 2.40). Gen 3x1 (before fix) Gen 3x1 (after fix) Gen3x4 (before fix) Gen3x4 (after fix) pl_link_up 150us 218us 39us 39us dl_link_up 634us 253us 76us 76us
6407 - PCIe for Nexus FPGAs: Could you please explain the 2 Adaptive Equalizer namely RL2Plus and SS_LMS?
There is not much explanation about it; however, it is general knowledge that we can check on the web related to the adaptive algorithm namely: SS-LMS and RL2plus. In summary, SS-LMS is a successful algorithm if there is sufficient spectral ...
6878 - Does Lattice implement inclusive language principles on their documents?
Inclusive Language FAQ Lattice has adopted inclusionary language principles for newly created documents. In some cases, this approach leads to differing terminology between documents and underlying tools and other items. The following terms are now ...
6863 - PCIe for Nexus FPGAs: Is there other way to access the PCIe PLL status and pipe_rstn aside from LMMI?
For now, unfortunately it can only access via LMMI. PLL status -> 0xF200 pipe_rstn -> 0xF004
7316 - All Nexus / PCIe: PCIe assignment of 2GB BAR size for 64-bit BAR addressing.
Description: There is a known bug in the PCIe IP GUI wherein the 64-bit BAR addressing requires that the BAR size be >/= 4 GB only. Solution: As a workaround, the user can write the Resizable BAR Capability Configuration (0,1,2,3,4,5) using LMMI or ...
6254 - All Nexus / PCIe: How to use and implement the external reference clock (SD_EXTy_REFCLKn) of the PCIe core IP on Radiant Software?
Description: Example Implementation:
6250 - PCIe for Nexus FPGAs: In PCIe X4 IP Core, I have selected AHB_LITE as the Data Interface Type. What is the clock domain for this interface?
clk_usr_o originates from the PCIe Core, bypassing the PCIe Soft IP. It serves as an output to an external pin. Additionally, there are two input clocks for the Soft IP: clk_usr_i at 250 MHz and clk_usr_div2_i at 125 MHz.
6247 - PCIe for Nexus FPGAs: How to access PCIe peripherals using AHB-lite interface?
Solution: DMA support must be enabled to access the PCIe endpoint through AHB-lite. The DMA (Direct Memory Access) support has an option to enable efficient data transfer when the device acts as an initiator or a master. For more information, refer ...
6240 - PCIe for Nexus FPGAs: Encountered error in test bench using Radiant's IP core that is compiled in XCELIUM. How to fix it?
Description: The error typically happens when GSR and PUR primitives are not included in the design. Some IP core uses GSR and PUR primitives as designed to mimic the device Power-on scenario. In this case, without these primitives, the simulation ...
6236 - PCIe for Nexus FPGAs: What is the total amount of PCIe interfaces in CertusPro-NX-100 with different lanes?
The PCI Express Link Layer Quad for all CertusPro-NX devices has four PIPE interfaces that can be used in different number of links. This can provide the maximum flexibility, depending on the bandwidth of the application requirements. The PCIe link ...
7234 - PCIe for Nexus FPGAs: Why is PCIe IP downgraded to x1 lane even though it is configured as x1 lane?
Description: This is a potential bug in the GUI setup Solution: To workaround the issue, use LMMI to write '1' (configured to max width x1) on bit [18:16] of register 0x20.
6609 - All Nexus/PCIe: What clock does "link[LINK]_perst_n_i" and "link[LINK]_rst_usr_n_ " synchronized with?
In TLP interface, both perst_n and rst_usr_n are asynchronous from the user perspective. There are built-in synchronizers for these resets.
7002 - PCIe for Nexus FPGAs: Where to download the PCIe Demo driver source code for Linux and Windows?
Description: The PCIe demo driver source code for Linux and Windows can be downloaded from below link: Scroll down the page and choose the appropriate PCIe Demo designs from the list. ...
7192 - PCIe for Nexus FPGAs: Why do PCIe Configuration Space registers (i.e. Device ID, Vendor ID, etc) not persist after first enumeration?
Description: The PCIe IP v1.1 contains a bug in which the Device ID and Vendor ID values in the GUI do not reflect in the configuration space. Solution: As a workaround, users could configure the IDs in respective registers. This is done through the ...
6979 - PCIe for Nexus FPGAs: Does the vc_tx_valid_i can be delayed (insert 3 clock cycles) during long external memory read since the FPGA lose the access for some clocks?
Description: The vc_tx_valid_i should not be delayed or do insertion of the 3 clock cycles gap within packets as it affects the validity of the data thus it is forbidden to insert such delay. This cannot be use as a workaround for the long external ...
7191 - CertusPro-NX/PCI Express: How to set APB address of PCI Express IP?
Solution: For the APB interface, the c_apb_paddr_i is as described in the UG. Example of an address:
6978 - PCIe for ECP5: How to disable the Advanced Error Reporting (AER) of the ECP5 PCIe IP ?
Solution: Untick the box of "Use Advanced Error Reporting" in the PCIe IP GUI to disable the AER.
7190 - CertusPro-NX/PCI Express: Can the clock signal link[LINK]_aux_clk_i be left open in case L1 is not used?
Solution: It is best to turn it off by writing '0' as per PCIe Specification.
7189 - CertusPro-NX/PCI Express: What is the AHB slave interface Endianness completion format for PCIe x4?
Description: Bytes 8-11 here illustrate Memory TLP, which contains Address field. It could be other fields, depending on the TLP type. Bytes 12-15 here show the payload field for 3-DW header TLP. It could be a 4th-DW header field, or it does not ...
6976 - PCIe: How to view the PCIe configuration space on a specific domain in Linux machine?
Description: The users have to use lspci command. To get more information about the command list, invoke sudo lspci -h. Solution: From the example scenario below. -x is used to display the standard part of the configuration. -s is used to display the ...
6961 - PCIe for Nexus FPGAs: Does PCIe IP supports full PCIe X1 component/block and configuration via LMMI (without using GUI)?
Description: There are some parameters that cannot be configured using LMMI. Example, in these 2 parameters: a) Target Link Speed – this is possible. The LMMI write needs to happen before PHY out of reset b) Use TLP Interface – this is not possible ...
6934 - PCIe for Nexus FPGA: How to write the Link Layer Configuration Space Registers on PCIe device?
Solution: 1. Defining the usr_lmmi_offset_i [16:2] a. usr_lmmi_offset_i [16] == selects between Link Layer or PHY register access b. usr_lmmi_offset [15:2] == refer to FPGA-IPUG-02126 à word aligned offset of base + offset address 2. Write “1’b0” on ...
6927 - PCIe for Nexus FPGAs: Using the Lattice CertusPro-NX PCIe x4 IP Core and the AXI4-Stream interface, what is the latency of read and write access through the APB interface across the Link Layer registers, Configuration Space Registers, and the Soft
Here is the latency table of the read & write through the APB interface for CertusPro-NX:
6923 - PCIe for Nexus FPGAs: Which TLP types from the provided table are not supported by the macro/IP?
All is supported except for the locked requests.
6919 - Nexus / PCIe: How to determine the total DW of TLP to be received by link[LINK]_rx_data_o?
Description: Referring to the TLP fields of the PCI-Express Base Specification (https://pcisig.com/specifications), the ‘Fmt’ will determine the desired format of TLP.
6104 - PCIe: Does Lattice FPGA's PCIe SGDMA memory addressing allows beyond 4GB?
Description: Technically there is no restriction on Lattice's FPGAs which makes us not allow memory addressing beyond 4GB. That is more on the driver side. There are some FPGA solutions which already has beyond 4GB, CrossLink-NX, Certus-NX, and ...
6447 - CertusPro-NX PCIe: Does both Quad 0 and Quad 1 support hard IP block of PCIe link layer?
CertusPro-NX only supports the hard IP block PCIe link layer on Quad 0. For more information, refer to second paragraph of section '11.1. PCI Express Mode' on FPGA-TN-02245.