6976 - PCIe: How to view the PCIe configuration space on a specific domain in Linux machine?

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• 6900 - PCIe for Nexus FPGAs: How can the PCIe configuration space settings in the RTL of the demo be interpreted?

  Description: To understand the RTL formatting of the PCIe configuration space in the Nexus' PCIe demos, please refer to the following details. Figure 1 illustrates the initialization of the PCIe configuration space in the Nexus' demo.

• 3606 - LatticeECP3: Can we change the DEVSEL parameter to SLOW for the PCIe IP (Peripheral Component Interconnect Express) configuration space?

  No, the PCIe (Peripheral Component Interconnect Express) base specification clearly says that the DEVSEL TIMING parameter does not apply to PCIe Express Configuration space and is hardwired 0 by default. This means the DEVSEL TIMING parameter is ...

• 7192 - PCIe for Nexus FPGAs: Why do PCIe Configuration Space registers (i.e. Device ID, Vendor ID, etc) not persist after first enumeration?

  Description: The PCIe IP v1.1 contains a bug in which the Device ID and Vendor ID values in the GUI do not reflect in the configuration space. Solution: As a workaround, users could configure the IDs in respective registers. This is done through the ...

• 6934 - PCIe for Nexus FPGA: How to write the Link Layer Configuration Space Registers on PCIe device?

  Solution: 1. Defining the usr_lmmi_offset_i [16:2] a. usr_lmmi_offset_i [16] == selects between Link Layer or PHY register access b. usr_lmmi_offset [15:2] == refer to FPGA-IPUG-02126 à word aligned offset of base + offset address 2. Write “1’b0” on ...

• 7002 - PCIe for Nexus FPGAs: Where to download the PCIe Demo driver source code for Linux and Windows?

  Description: The PCIe demo driver source code for Linux and Windows can be downloaded from below link: Scroll down the page and choose the appropriate PCIe Demo designs from the list. ...