6254 - All Nexus / PCIe: How to use and implement the external reference clock (SD_EXTy_REFCLKn) of the PCIe core IP on Radiant Software?

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• 6220 - CertusPro-NX: How to select the external SerDes reference clock (SD_EXT_x_REFCLKn) of MPCS?

  By using MPCS, the user does not need to specify the location of SD_EXT_x_REFCLKn using a constraint file. Example snippet of the implementation: DIFFCLKIO DIFFCLKIO_inst ( .CLKIN0_P (sd_ext_0_p_i), .CLKIN0_N (sd_ext_0_n_i), .CLKIN1_P (), .CLKIN1_N ...

• 6250 - PCIe for Nexus FPGAs: In PCIe X4 IP Core, I have selected AHB_LITE as the Data Interface Type. What is the clock domain for this interface?

  clk_usr_o originates from the PCIe Core, bypassing the PCIe Soft IP. It serves as an output to an external pin. Additionally, there are two input clocks for the Soft IP: clk_usr_i at 250 MHz and clk_usr_div2_i at 125 MHz.

• 6240 - PCIe for Nexus FPGAs: Encountered error in test bench using Radiant's IP core that is compiled in XCELIUM. How to fix it?

  Description: The error typically happens when GSR and PUR primitives are not included in the design. Some IP core uses GSR and PUR primitives as designed to mimic the device Power-on scenario. In this case, without these primitives, the simulation ...

• 7762 - PCIe: Does Lattice ECP3 Serdes reference clock compatible with HCSL driver?

  For ECP3, the recommendations for the SerDes Reference Clock Interface are based on the LVDS and LVPECL standards and these are guaranteed to have no issues with the 100-ohm termination. You may refer to the Electrical Recommendations for Lattice ...

• 7193 - PCIe for Nexus FPGAs: How to generate MSI Interrupts with PCIe x1 IP core?

  Solution: To successfully use the MSI Interrupt, the user needs to perform the workaround below. Uncheck the box for "Disable Legacy Interrupt" to enable the Legacy Interrupt. This is a controller code requirement. 'MSI pending bit' = 1 alone does ...