PCIe: Procedures to run CertusPro-NX PCIe simulation using Cadence Xcelium simulator.

1. During PCIE_X4 IP generation in Lattice Radiant tool, follow below GUI settings.

   i) Simulation Reduce Timeout = 1

   ii) Register Interface Type = LMMI 

   iii) Non-DMA mode: Data Interface Type = TLP

       DMA Enabled mode: Data Interface Type = AXI_MM

    

2. Ensure the Testbench Files are generated during PCIE_X4 IP generation.

    

3. Click Radiant's 'Simulation Wizard' to initiate the wizard and create a new simulation project by entering your "Project name'.  

   

4. Click icon ‘Add simulation source files’, add the tb_top.v file.

     

5. Select tb_top as Simulation Top Module.

    

6. Follow the below simulation settings. Set Default Run to 0.

     

7. QuestaSim Lattice-Edition will be launched, close this window because Xcelium-OEM Edition will be launch in later step.

    

8. Compile the ‘lfcpnx’ library for Xcelium-OEM full version.

    i) The existing device library is compiled for Questasim Lattice-Edition, so it is necessary to recompile for Xcelium full version.

    ii) In Radiant Tcl Console pane, execute below command (use Radiant 2025.1 or onwards).

        cmpl_libs -64 -sim_path <Xcelium_FullVersion_path> -sim_vendor cadence -device lfcpnx -target_path <your_target_path>

        Example: 

       cmpl_libs -64 -sim_path /tools/dist/cadence/XCELIUM/XCELIUM23.03_g453/Linux/tools.lnx86/bin -sim_vendor cadence -device lfcpnx -target_path /home/CPNX_PCIe/SIM1

9. Open the generated “<project>.f” in your simulation project folder, edit the -reflib as below.

    From: 

    

    To: 

    

     Note: The lfcpnx folder at line#2 above is the library compiled during Step 8.

                 Line#10 is to save the simulation log file (it is optional).

10. Run your <project>.f file using Xcelium 

Example: xrun -v_XCELIUM23.03_g453 -64bit -f /home/CPNX_PCIe/SIM1/SIM1.f

11. Wait for the simulation to complete.

      

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