7191 - CertusPro-NX/PCI Express: How to set APB address of PCI Express IP?

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• 6447 - CertusPro-NX PCIe: Does both Quad 0 and Quad 1 support hard IP block of PCIe link layer?

  CertusPro-NX only supports the hard IP block PCIe link layer on Quad 0. For more information, refer to second paragraph of section '11.1. PCI Express Mode' on FPGA-TN-02245.

• 7078 - CertusPro-NX/PCI Express: Why would the host PC crash when running the PCIe DMA Throughput Demo of CertusPro-NX?

  Description: The following operation will causes the host PC to crash. - Run Batch Test with Write Operation checked. Solution: Please use the 'Throughput Test' tab instead of the 'Batch Test' tab as it will causes the GUI to crash. Please unselect ...

• 1061 - Lattice All FPGAs: Which device is the minimal device needed to support PCI Express x1 and x4 core?

  The PCI Express x1 and x4 IP Core is supported by both SC and ECP2 device families. The minimal ECP2M device needed to support the core is LFE2M-20E-6F484C, and the minimal SC device needed is LFSC3GA15E-6F900C. Newer Lattice FPGA families that ...

• 6927 - PCIe for Nexus FPGAs: Using the Lattice CertusPro-NX PCIe x4 IP Core and the AXI4-Stream interface, what is the latency of read and write access through the APB interface across the Link Layer registers, Configuration Space Registers, and the Soft

  Here is the latency table of the read & write through the APB interface for CertusPro-NX:

• PCIe: Procedures to run CertusPro-NX PCIe simulation using Cadence Xcelium simulator.

  1. Create a new Radiant project targeting CertusPro-NX. 2. Select IP on Server and install the latest version of PCIE_X4 IP, if it is not yet installed. 3. Switch to IP on Local, double-click PCIE_X4 and enter your desired Component name. 4. ...