7191 - CertusPro-NX/PCI Express: How to set APB address of PCI Express IP?
Solution:
For the APB interface, the c_apb_paddr_i is as described in the UG.
Example of an address:
Decode the readdata (c_apb_prdata_o) as below:
[15:8] = Bus number
[7:3] = Device number
[2:0] = 3’b0 (Function number)
add the 0x28000 base address to the CSR base address as shown below:
CSR base address + base offset address + register offset address
0xC5200000 + 28000 + 0x4 = 0xC5228004
Related Articles
6447 - CertusPro-NX PCIe: Does both Quad 0 and Quad 1 support hard IP block of PCIe link layer?
CertusPro-NX only supports the hard IP block PCIe link layer on Quad 0. For more information, refer to second paragraph of section '11.1. PCI Express Mode' on FPGA-TN-02245.6927 - PCIe for Nexus FPGAs: Using the Lattice CertusPro-NX PCIe x4 IP Core and the AXI4-Stream interface, what is the latency of read and write access through the APB interface across the Link Layer registers, Configuration Space Registers, and the Soft
Here is the latency table of the read & write through the APB interface for CertusPro-NX:DisplayPort TX IP Version 2.1.0 does not support back-to-back video input without blanking interval
Description DisplayPort TX IP version 2.1.0 requires the video input to provide blanking interval between active horizontal video lines to ensure correct video data packing. Failure symptoms include no video image output or black screen, even though ...7078 - CertusPro-NX/PCI Express: Why would the host PC crash when running the PCIe DMA Throughput Demo of CertusPro-NX?
Description: The following operation will causes the host PC to crash. - Run Batch Test with Write Operation checked. Solution: Please use the 'Throughput Test' tab instead of the 'Batch Test' tab as it will causes the GUI to crash. Please unselect ...1061 - Lattice All FPGAs: Which device is the minimal device needed to support PCI Express x1 and x4 core?
The PCI Express x1 and x4 IP Core is supported by both SC and ECP2 device families. The minimal ECP2M device needed to support the core is LFE2M-20E-6F484C, and the minimal SC device needed is LFSC3GA15E-6F900C. Newer Lattice FPGA families that ...