1329 - Is it possible to implement two full X4 PCIe endpoints in one device? I am interested in a non transparent bridge application...

• Related Articles

• 2174 - LatticeECP3/DDR3 SDRAM Controller: How can I integrate two (or more) DDR3 IP cores into one LatticeECP3 device?

  Integrating multiple DDR3 interfaces into a LatticeECP3 device can be done using one of the following cases depending on the locations of the DDR3 interfaces. 1. When locating all DDR3 interfaces on one side (either the left or right side): Sharing ...

• 766 - SERDES can run at either full-data-rate mode or half-data-rate mode What is the difference between the two?

  With the same reference clock frequency, if the SERDES is configured to half-data-rate mode, the SERDES data rate is only half of the data rate supported in the full-data-rate mode. It is useful when different rates are used for different channels in ...

• PCIe: Procedures to run CertusPro-NX PCIe simulation using Cadence Xcelium simulator.

  1. During PCIE_X4 IP generation in Lattice Radiant tool, follow below GUI settings. i) Simulation Reduce Timeout = 1 ii) Register Interface Type = LMMI iii) Non-DMA mode: Data Interface Type = TLP DMA Enabled mode: Data Interface Type = AXI_MM 2. ...

• 2684 - DDR3 IP: Why do I have two top-level wrappers inside a DDR3 IP core package generated from IPexpress ? Which one should I use for my design?

  The DDR3 IP core package includes two top-level wrapper files in two different places using the same name, ddr3_sdram_mem_top_wrapper.v or .vhd. One of them which is located in the directory "ddr_p_eval\<user_name>\impl" is used solely for the core ...

• 6961 - PCIe for Nexus FPGAs: Does PCIe IP supports full PCIe X1 component/block and configuration via LMMI (without using GUI)?

  Description: There are some parameters that cannot be configured using LMMI. Example, in these 2 parameters: a) Target Link Speed – this is possible. The LMMI write needs to happen before PHY out of reset b) Use TLP Interface – this is not possible ...