7158 - CertusPro-NX/PCI Express: Why does PCIe Gen3x1 and Gen3x4 simulation takes longer time to link-up?

• Related Articles

• 6447 - CertusPro-NX PCIe: Does both Quad 0 and Quad 1 support hard IP block of PCIe link layer?

  CertusPro-NX only supports the hard IP block PCIe link layer on Quad 0. For more information, refer to second paragraph of section '11.1. PCI Express Mode' on FPGA-TN-02245.

• 6236 - PCIe for Nexus FPGAs: What is the total amount of PCIe interfaces in CertusPro-NX-100 with different lanes?

  The PCI Express Link Layer Quad for all CertusPro-NX devices has four PIPE interfaces that can be used in different number of links. This can provide the maximum flexibility, depending on the bandwidth of the application requirements. The PCIe link ...

• 7078 - CertusPro-NX/PCI Express: Why would the host PC crash when running the PCIe DMA Throughput Demo of CertusPro-NX?

  Description: The following operation will causes the host PC to crash. - Run Batch Test with Write Operation checked. Solution: Please use the 'Throughput Test' tab instead of the 'Batch Test' tab as it will causes the GUI to crash. Please unselect ...

• 2691 - PCI Express IP: Why does the TXPLL no longer lock in my PCIe design when I migrate to the latest version of the Lattice PCI Express IP?

  Version 5.2 of the Lattice PCI Express IP includes an update to use the reset sequence (instead of the 4ms reset timer) requiring the reference clock from the SERDES to be enabled to the fabric. You likely use a .txt file from an earlier version ...

• 1061 - Lattice All FPGAs: Which device is the minimal device needed to support PCI Express x1 and x4 core?

  The PCI Express x1 and x4 IP Core is supported by both SC and ECP2 device families. The minimal ECP2M device needed to support the core is LFE2M-20E-6F484C, and the minimal SC device needed is LFSC3GA15E-6F900C. Newer Lattice FPGA families that ...