6878 - Does Lattice implement inclusive language principles on their documents?

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  Lattice currently recommends the following for implementing Gigabit Ethernet interfaces: CertusPro-NX FPGAs: Use SERDES-based SGMII or RGMII Certus-NX, MachXO5-NX, and CrossLink-NX: Use RGMII These recommendations are based on updated LVDS-based ...

• 1329 - Is it possible to implement two full X4 PCIe endpoints in one device? I am interested in a non transparent bridge application...

  It is possible to implement several x4 PCIe endpoints in a single Lattice device. Here are some possible solutions. LatticeECP3 devices LFE3-70 and 95 can support 2 x4 PCIe endpoints LFE3-150 can support up to 4 x4 PCIe endpoints LatticeECP2M devices ...

• 4012 - [Lattice ECP3] PCI Express Endpoint Core IP: How does the Lattice PCIe (Peripheral Component Interconnect Express) IP core issue multiple MSI (Message Signaled Interrupts) when multiple MSI request bits are set in the end application?

  Description: The Lattice PCIe (Peripheral Component Interconnect Express) IP (Intellectual Property) core asserts all MSI one after the other. The Lattice PCIe (Peripheral Component Interconnect Express) IP (Intellectual Property) can handle up to 8 ...

• 1723 - CPRI:  Can Lattice CPRI IP core (Common Public Radio Interface) support auto-negotiation?  

  Lattice CPRI IP core (Common Public Radio Interface) itself provides the auto-negotiation function. There is a state machine that will automatically go through a searching state from one line rate to the next line rate, eventually it will find the ...

• 2244 - LatticeECP3: I need to use four chip select signals while the Lattice DDR3 controller IP core supports only up to two. Can I extend the number of chip select from the core?

  Description: No. Lattice DDR3 controller IP core does not support more than 2 chip selects. The IP core was designed and validated to support upto two ranks of DDR3 memory configurations. Since each rank is controlled by a corresponding chip select ...