I/O (HPIO, WRIO)
6398 - CertusPro-NX: Does High Performance IO supports hot socketing?
The Certus-Pro NX HP IOs does not support hot socketing.
2945 - Power Manager II: Why do I see a short (150ns or longer) logic zero glitch on my Power Manager Supervisory Equation open-drain-output shortly after power-up?
Description: This is usually the result of setting the Reset level in the PINS window to Set Low / Don't Care; combined with the logic of the Supervisory Equation setting the output High. If the logic High condition passes through more than a single ...
6016 - MachXO2/XO3/XO3D: Do we have hot socketing specification in LVDS I/O standard?
There’s no difference between single-ended and differential I/O. The hot socketing specification remains the same.
6323 - MachXO3: Can the HCSL to LVDS Translation be done in MachXO3 Device?
The MachXO3 can accept with HCSL output when either internal or external parallel termination is ON, so that can convert the current drive to voltage drive, and our differential input buffer can detect the 0/1. And then, the user can use true LVDS to ...
2933 - Power Manager II: Why do I see a short (150ns or longer) logic zero glitch on my Power Manager open-drain output at the beginning of the sequence?
Description: This is usually the result of setting the Reset level in the PINS window to Set Low / Don't Care; combined with the first step of the sequence setting the output High. If the output is set High in the second step of the sequence; then ...
6315 - Lattice Radiant: What is drive strength of an output when set to 50RS and how it is applied?
50RS is considered a driver that consumes ~8mA (This can change depending on the device family). Other drive strengths cannot give 50-ohm matching.
2879 - MaxhXO2: Are all pins defined as NC really not connected to anything? So, if a breakout was going to route through NC pins in MachXO2, there would not be an issue?
Pins labeled as NC are not connected. The package pins/balls are floating. However, care must be taken on a device with NC if future pin migration is considered. On a lower density device with the same package, when moving to a higher density device, ...
2142 - [ispMACH 4000]: What is the reason behind the high supply transients during startup for the ispMACH 4000 device?
High transients during startup are because of supply sequencing used on the board, resulting in temporary leakage in the I/O buffer of the device. To minimize the transient current during power-on, configure the CPLD I/Os to a pull-up or float state. ...
2127 - Should pullups be enabled or disabled for PCI outputs for PCI33?
Per the PCI specification pullups are to be on the motherboard, not on the add-in cards. Since pullups are enabled by default for Lattice devices, the user should explicitly disable them for the PCI output signals. Below is an example constraint from ...
2118 - Lattice ECP3: Can I connect an external Low Voltage Differential Signal 2.5V (LVDS25) clock output to a Lattice ECP3 DDR3 bank which is a 1.5V VCCIO bank?
Yes, the user can drive an external Low Voltage Differential Signal (LVDS) clock generator to an input pair of the LatticeECP3 1.5V VCCIO bank. Although the Lattice ECP3 LVDS25 is characterized in 2.5V and 3.3V, the user can safely use an external ...
2117 - MachXO2: Can I connect the JTAGENB pin of the MachXO2 device directly to the VCC or GND?
The JTAG ENABLE pin of MachXO2 is an optional input pin that can be used to control the function of the ispJTAG port during user mode. By default, the JTAGENB pin is a user I/O while the 4-wire ispJTAG port is used as a dedicated programming port. ...
2116 - Lattice ECP3: The availability and cost of a 1.5V clock driver make it an unattractive solution for driving the reference clock input of the DDR3 memory interface, are there any alternatives?
Several alternatives can be used to drive the LatticeECP3 DDR3 reference clock input: 1. Use an LVDS clock driver and connect directly to the DDR3-dedicated PLL input pair. LVDS25 is a compatible I/O type that can be used in a 1.5V VCCIO bank. This ...
7312 - Crosslink: How to implement OPENDRAIN on Bi-Directional I/O port in CrossLink device?
CrossLink I/O does not have OPENDRAIN support for bi-directional pins. This feature is limited by the device hardware itself. However, this product still offers OPENDRAIN support but only limited to output ports only.
5945 - Silicon Image: Can we adjust TMDS swing level of the Tx output port 1 and 2?
User could not change it due to register limitation. User only have 3 bits to change swing setting in tx1 and tx2, that means only 0-7 is acceptable.
4325 - iCE40 LP: How to calculate the internal pull up resistor value of an iCE40 LP 1K device?
Current rating for VCCIO 3.3 from data sheet (Min 11uA Max128uA) For LVCMOS33 -> Vih(min) is 2.0V Hence Rp = 3.3V - 2.0V / (11uA) = 18.18K Ohm For LVCMOS33 -> Vih(min) is 2.0V Hence Rp = 3.3V - 2.0V / (128uA) = 10.15K Ohm
538 - LatticeECP2/M / LatticeECP3 / LatticeSC/M: What is the recommended connection for the XRES pin for the LatticeECP2/M, LatticeECP3, and LatticeSC/M devices?
LatticeECP2/M, LatticeECP3, and LatticeSC/M devices require a single external resistor which is used to create the bias currents for the IO. This resistor is connected between the XRES pin and ground. The device will not initialize and configuration ...
7271 - MACHXO3: Why does the Diamond software still allow the LVCMOS10R33 and LVCMOS10R25 IO types on speed grade -5 of MachXO3LF when the documentation says speed grade -6 devices only support them?
Solution: The datasheet only shows speed grade -6 support for LVCMOS10R33 and LVCMOS10R25 IO types because it can cover all the frequency range up to the fmax parameter of speed grade -6 devices. The Diamond software still allows LVCMOS10R33 for ...
6252 - MachXO3: Are the M-LVDS receivers for XO3L/LF either Type 1 or Type 2?
M-LVDS input receiver complies with ANSI TIA/EIA-899 and also complies with Lattice input leakage current requirements. TIA/EIA-899 describes two types of input receivers, Type 1 and Type 2. Type 1 receivers have the cross-over set to 0 + 50 mV ...
5918 - MachXO2: What happens to the Lattice FPGA if we break the recommended Logic Signal Connections that shall not exceed a maximum of n * 8 mA?
FPGA’s including Lattice FPGA and other VLSI circuits are connected using thin-film metallic conductors and they are subject to increasingly high current densities. Under these conditions, electromigration can lead to the electrical failure of ...
7256 - How do we know the rise and fall time requirement for GPIO in FPGA?
Description : There is no such specification given for GPIO rise and fall time. Here are some general guidelines for GPIO in FPGA in general: 1. When dealing with faster rise/fall time, user needs to make sure it does not cause reflection and create ...
2676 - ECP3: Can output enable signal be used for 7:1 LVDS design?
For 7:1 LVDS design, it is usually used for unidirectional video data transfer. In Lattice's related reference designs -- RD1030/etc., data is driven to LVDS output pads through Output Buffer (OB) primitive To temporarily shut down the LVDS output ...
7248 - Lattice ECP5 : What is the VSSIO used for in the pinout file of ECP5?
Description: The VSSIO is the system ground or the ground reference voltage pin of the I/O pins. You can connect the VSSIO to the GND pin.
2082 - LatticeECP3: How to effectively use secondary region clock in LatticeECP3 devices?
Description: For LatticeECP3 devices, there are a total of 8 SECONDARY clocks. Each of the SECONDARY clocks can be further divided into REGION clock. The SECONDARY clocks are divided into different sized REGIONs depending on the device density. For ...
7215 - How does enabling HYSTERESIS impact the behavior of GPIO inputs?
Description: Hysteresis is implemented by separating the rising and falling edge threshold trip points. GPIO with no hysteresis has a common decision point on rising and falling edges - The decision point is between VIL(max) and VIH(min) depending on ...
5884 - All FPGA: How I can generally compare the difference between SLOW and FAST of the SLEW RATE settings?
Description: Using the RAMP data in the IBIS you can compare the Slew Rate between SLOW and FAST, try to understand the document using the notes and legends provide especially "Naming Conventions" in the upper part of the document and be able to read ...
4028 - iCE40 LP/HX: Are the NC (NOT CONNECTED) pins on iCE40 devices internally connected?
The NC (NOT CONNECTED) pins of iCE40 devices are not connected internally.
5869 - Platform Manager2 and ASC devices: Can VMON and VMONGS pins be left floating when they are not in use?
VMONx/VMONGS pins can be left floating when not in use. But it's also a good practice to ground the VMONGS pin and put a pull-down on the VMON pin to make it easier to do some workaround if you decided to use the VMONx/VMONGS pins again.
7211 - Why is PULLMODE set to NONE when port is configured as output?
Description: There is no PULLMODE for output-only ports, therefore all output pins PULLMODE will be fixed to 'NONE' in the tool. For bi-directional pins, PULLMODE will be relevant, and thus it will be set to 'NONE' when the bi-directional pin acts as ...
5867 - ispMach400: In BSDL file, if any IOs are configured as "Input Only"; Does the device needs to be erased and re-programmed to bi-directional pin the same as the output?
The Input only IO, do not need to be erased and reprogrammed to be bi-di IO. Only output only IO needs it.
2070 - Power Manager II: What is the POR state of I2C controlled input and output pins in POWR1014A?
Description:Input pins that are "controlled" by I2C remain in high impedance (high-Z) state as they are not bidirectional pins and they are always inputs. Output pins that are controlled by I2C, will follow the behavior as listed in Table "I2C ...
5835 - ispMACH 4000: Why did the ispMACH datasheet not provide rise and fall time?
Lattice FPGA inputs are very fast, thus are very sensitive to noise, there is no Schmitt trigger or hysteresis option. A perfect monotonically rising edge could an arbitrarily slow rise time, but the reality is noisy. A good rule of thumb for the ...
6996 - iCE40: Does Bank 3 have any internal pull-up resistors for iCE40?
Details: GPIOs found in Banks have no internal pull-ups, only Banks 0-2 have internal pull-ups. Since they do not have any internal pull-up in Bank 3, we recommend tying the unused PIO pins in Bank 3 to a known logic or driving them with disabled ...
7197 - All Nexus: What is the default drive strength for I/O pins?
Description: This article lists the default drive strength for different IO_TYPE for Nexus products. Solution: For Nexus products, these are the default drive strength set in Radiant SW according to the IO_TYPE, and they are applicable for both Wide ...
2045 - [ispMACH 4000]: I have 75 5V inputs to an ispMACH 4000 device. Which I/O type should I use between LVTTL or LVTTL_5V?
Description: Two 5V support options, “PCI_5V” and “LVTTL_5V” were added to the supporting I/O type constraint list for the ispMACH™ 4000 device families. Since the LVTTL I/O type's maximum VIH is 3.6V, you must use the LVTTL_5V I/O type to support 5V ...
2598 - Can Lattice FPGAs use a general purpose I/O to assert it's own PROGRAMN pin?
Lattice does not recommend using the FPGA's general purpose I/O to assert its own PROGRAMN pin. There is risk the FPGA may not restart after the first attempt to assert the PROGRAMN pin. The PROGRAMN pin can inadvertently be pulled low, which can ...
2588 - ECP3: How can I determine the exact number of hot-socketable I/O on a LatticeECP3 device?
Whether an I/O pad is hot-socketable or not is determined by the location of the pad instead of the bank where the pad is included. All general purpose I/O pads located on the top and bottom sides of LatticeECP3 devices are hot-socketable.These are ...
6975 - MachXO3D: The VCCIO0 ( Bank 0 ) is tied to 1.8V making the JTAG interface 1.8 V. Can I pull the TDO output higher ( 2.5V, 3.3V )than the VCCIO?
No, the user the customer needs to Change the VCCIO0 to the set voltage( 2.5V, 3.3V ) or Use a 1.8V to (2.5V, 3.3V ) level shifter.
6973 - [Avant-E] Radiant 2022.1: How to fix DQS/DQ grouping issue?
Solution: We have to implement the controller as x32 data bus and in that case the pinout of AVANT-E eval board rev C can be used. Radiant works with that complete pinout so both channels must be driven using the x32 configuration.
7178 - CertusPro-NX: Why are FPGA I/O lines "zero" by default? How to pull them to 'high' by default?
CertusPro-NX's I/O hardware default is weak pull-down, and it cannot be changed until it is powered up and loaded with bitstream. The only way to get those lines to be 'high' by default is by adding external pull-up resistor on the PCB board.
6169 - ispMACH4000: What is the difference between "LVCMOS33" and "LVCMOS33_5V"?
Description: The I/Os in the ispMACH 4000 are split into two banks. Each bank has a separate I/O power supply. Inputs can support a variety of standards independent of the chip or bank power supply. Outputs support the standards compatible with the ...
Next page