5884 - All FPGA: How I can generally compare the difference between SLOW and FAST of the SLEW RATE settings?
Description:
Using the RAMP data in the IBIS you can compare the Slew Rate between SLOW and FAST, try to understand the document using the notes and legends provide especially "Naming Conventions" in the upper part of the document and be able to read and understand the data provided.
Solution:
When checking the IBIS model, one should be familiar of the naming conventions of the I/O model. As an example, you can check the ramp data for MachXO2.
NAMING CONVENTIONS: |
LEGEND: |
Related Articles
1825 - What is the recommended slew rate with less duty cycle variations? <br>
The FAST or SLOW slew can cause as much as 5% duty cycle variation depending on the frequency and the load. The general recommendation is to use FAST slew rate for frequencies higher than MHz. At higher frequencies, FAST slew will show a more ...1066 - What are the hardware default settings of the ECP2/M sysCONFIG ports?
Basically, all the sysCONFIG pins have hardware default settings as standard LVCMOS IO configuration after power-up. When sysCONFIG pins act as driver, they are 8ma drivers when VCCIO8 @3.3V/2.5V/1.8V. They become 4ma pull up when VCCIO8 @1.5V/1.2V ...569 - ALL CPLD: Can changing the slew rate save power?
Description: Yes changing the slew rate can save uA dynamic power. This is a result of the signal transitioning faster between the Vil, Vih input thresholds. One warning the faster your edge rate the more SSO (Simultaneous Switching Output) and ...843 - What can I do to maximize the emulated LVDS data rate? <br>
Emulated LVDS will have maximum data rate near the device FMAX_IO frequency value if: the IOs are complimentary LVCMOS outputs (or have low timing skew) the IOs have similar rise and fall times the emulated LVDS output resistor network is placed ...3828 - iCE40: Is VPP_FAST on ICE40LP CM81 device supported?
No.VPP_FAST on ICE40LP CM81 device is not supported