6973 - [Avant-E] Radiant 2022.1: How to fix DQS/DQ grouping issue?

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• Can Avant Global Set/Reset Resources be analyzed through the Static Timing Analysis Tool on Radiant?

  Global Set/Reset resources cannot be analyzed in static timing analysis tool for both Nexus and Avant devices. For usage concerns and implementation of the mentioned resource, Users may refer to Global Set/Reset Usage for Nexus Platform App Note ( ...

• What is the difference between PCLKT and PLLT as dedicated PLL reference clock?

  Both PCLKT and PLLT are legal pin to use as PLL reference clock however there are differences on the clock paths that should take note in designing certain applications. PCLKT Pin: Provides a direct connection to the global and regional clock ...

• 6442 - MIPI for Nexus FPGAs: Does it allowed to assign MIPI signals (clock + data) across multiple different DQS group and implementing multiple MIPI signals (clock + data) in one DQS group?

  Yes the user can assign MIPI signals across different DQS groups. The current RD for CertusPro-NX implements the same idea. Example#1 - MIPI signals across multiple DQS groups: MIPI DSI-CSI2-OpenLDI-LVDS-Int_Bridge rx_clk_p_i MIPI_DPHY BDQ114 ...

• 2233 - LatticeECP3:  How to avoid a DQ output from becoming a PLL input when moving from a lower to a higher density device?

  The solution depends on whether or not the PCB has already been laid and the board's back is ready for use. In the schematic phase of the design, the solution is to move the DQ signal at pin T3 to another pin that is in the same DQ group that has DQ ...

• 2157 - [LatticeECP3] Will the LatticeECP3's read datavalid generation circuit work properly when I remove the VTT termination from the DQS pad?

  The datavalid generation circuit works properly as long as you provide the READ pulse input to the DQSBUF block in the right timing. LatticeECP3 devices have preamble detection function which is a level detection circuit instead of edge detection. ...