5945 - Silicon Image: Can we adjust TMDS swing level of the Tx output port 1 and 2?

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• 7211 - Why is PULLMODE set to NONE when port is configured as output?

  Description: There is no PULLMODE for output-only ports, therefore all output pins PULLMODE will be fixed to 'NONE' in the tool. For bi-directional pins, PULLMODE will be relevant, and thus it will be set to 'NONE' when the bi-directional pin acts as ...

• 2507 - Lattice Power Manager II: In the Power Manager device, is the output impedance of HVOUT port (in open drain mode) equal to that of the OUT port?

  Description: No, the impedance of HVOUT (in the open drain mode) and OUT port is not equal. The design for both the ports is different since HVOUT is designed for higher voltages (10V/12V) and OUT is designed for lower voltages(5.5V). For example ...

• 2676 - ECP3: Can output enable signal be used for 7:1 LVDS design?

  For 7:1 LVDS design, it is usually used for unidirectional video data transfer. In Lattice's related reference designs -- RD1030/etc., data is driven to LVDS output pads through Output Buffer (OB) primitive To temporarily shut down the LVDS output ...

• 879 - LatticeXP2: How can I drive mini-LVDS output on LatticeXP2 if mini-LVDS IO standard is not available?

  If user's design is using 50 ohm PCB trace and cable impedances, user can set the LatticeXP2 IO output type to LVDS and this will produce 400mv peak signal swing at the receiver's 100 ohm termination with proper common mode output voltage. The ...

• 2390 - LatticeECP3: Can all Tx PLL clocks of SERDES drive the primary clock routing directly?

  Description: No, only the Tx PLL half/full rate clocks in channel 0 of each SERDES quad may drive the primary clock routing directly. Eight primary clocks(CLK0~CLK7) may be used for LatticeECP3 devices. To drive the primary clock routing directly: ...