I/O (HPIO, WRIO)
3862 - iCE40: How to identify true (positive) and complementary (negative) ball functions for Low Voltage Differential Signaling (LVDS) inputs in iCE40 device?
The differential signals ending with 'B' in the Pinout file represent the positive end, and the differential signals ending with 'A' represent the negative end. For example, in the Pinout file, IOL_3A and IOL_3B are differential pins (DPIO). So, ...
6167 - [CrossLink] I/O: What is the max speed in MHz for subLVDS input when the banks are powered with 1.8V?
The maximum speed for subLVDS is 600MHz and this is the same when VCCIO is equal to 1.8V, 2.5V, and 3.3V.
5760 - [Platform Manager II]: In the Hot Swap sheet in Platform Designer, when Rs is set to 10 milliohms, the Fast Shutdown Limit can reach 20 A with max. However, in the Current sheet, when Rs is also set to 10 milliohms, the Fast Trip Point can reach 50
1. Fast Shutdown limit is also related to the Imax setting. 2. Fast shutdown Limit can also go up to 50A if Imax is set to 50A and above even with the same 10millohm resistor value. 3. Fast Shut Down Limit uses the IMON_F input which allows a ...
6509 - CertusPro-NX: NC(No Connections) pins of CertusPro NX should be connected to GND, or can be left open/floating?
No Connection pin is not actually connected on die so, either floating or ground connection can be applied.
6161 - iCE40 UltraPlus: How utilize Differential Input pairs on an iCE40 device?
For iCEcube2 compatible devices (LP/HX/LM/Ultra/UltraLite/UltraPlus), the user needs to use the SB_IO primitive and override the IO_STANDARD parameter to SB_LVDS_INPUT as shown in the rudimentary example below: SB_IO SB_IO_inst ( ...
1997 - Power Manager II: What is the buffer type for the POWR1220AT8 JTAG TDO pin and what voltage should the pull-up resistor be tied to for this pin?
The JTAG TDO pin is an LVCMOS output that is referenced to the voltage applied to the VCCJ pin. The voltage reference for this pin is shown in note 1 to the Digital Specifications table on page 1-11 of the ispPAC-POWR1220AT8 data sheet. There is no ...
5706 - MachXO2/XO3/XO3D: If the input voltage for input pins is over 3.6V or under -0.3V, will there be any problem?
The input signal of more than 3.6 but not greater than (VIHmax + 2 v ) and under -2 v is permitted. However, it should be around 20 ns only; otherwise, the device will be damaged. Please refer to the Device Data Sheet and look for DC and Switching ...
2516 - MachXO:
What is the meaning of "I/O Tristate Voltage Applied" and "Dedicated Input Voltage Applied" specified in the Absolute Maximum Ratings section of MachXO data sheet?
Solution: There are two cases where an IO pad is driven by an external source. One is the case of a dedicated input pad, and the other is a bi-directional IO pad in which its output can be tri-stated. The "Dedicated Input Voltage Applied" and "I/O ...
6502 - Certus-NX: What is the Maximum Current per bank?
Description: The maximum 64 mA per bank (8 IO with 8 mA) applies when selecting # of IO switching simultaneously. If desired is to use 16 mA with 8 IO switching, the overall junction temperature will be 2X higher. The source and sink current will ...
5705 - Diamond 3.10 and MachXO3: How to select "N/A" when setting all banks in 3.3V and need to assign input buffers LVTTL33?
Solution: Under this condition, the Hysteresis is supported. In the Diamond software, SMALL will be the default value. For more information, please refer to the MachXO3 sysIO Usage Guide under Table—mixed Voltage Support for LVCMOS and LVTTL I/O ...
5703 - MachXO2: Can XO2 IO buffer output mini-LVDS?
XO2/XO3 can support mini-lvds by using an external resistor to achieve the common-mode voltage and voltage swing that will act as mini-lvds
2513 - Can LatticeECP3 LVDS25 be driven by an LVDS18 output of a transmitter device? How about the other way around?
LVDS is an I/O signaling characterized with minimum/maximum differential voltages along with a common mode voltage. LVDS signaling is, therefore, independent from a supply voltage. For an external LSVD18 transmitter to drive LatticeECP3 LVDS25: The ...
241 - IO Simulation: How to simulate open drain IO/s?
An open drain IO drives output high as a 'Z' and drives low as a '0'. These IOs are often used when multiple devices are connected to a bus. On devices that do not have an open drain option, you can simulate an open drain circuit using an OE on the ...
5653 - iCE40 Ultra/UltraLite: What is the accuracy of the 48MHz internal oscillator (FCLKHF) at room temperature 20 deg C and 25 deg C as well as 50 deg C? In the datasheet, I only found +- 10% but I need more information that is specific.
If you refer to FPGA-DS-02008 otherwise known as iCE40 UltaPlus Family Data Sheet, Section 4.15. Internal Oscillators, it is described in Table 4.11 in the parameter description of the said temperature ranges such that for Commercial Temp, the +/- ...
5645 - MachXO2/MachXO3 :Are there any power supply sequence requirement for MachXO2 and MachXO3 devices?
POR is controlled by VCC and VCCIO0. As such, these banks should be brought up first. The typical I/O behavior during power-up is described below: The internal power-on-reset (POR) signal is deactivated when VCC and VCCIO0 reach VPORUP level. This is ...
5602 - iCE40: What is the required VPP_2V5 voltage if NVCM programming is not used?
From note 4 on page 28 of FPGA-DS-02008, VPP_2V5 can optionally be connected to a 1.8 V (+/-5%) power supply in Slave SPI Configuration modes subject to the condition that none of the HFOSC/LFOSC and RGB LED driver features are used. Otherwise, ...
1946 - [LatticeECP3/LatticeECP2/MachXO2/XP2] Are there hardware resources that helps me to achieve my input HOLD requirements?
Yes, there are such resources in select Lattice devices. There are three different resources that you can use to do this. They are: 1). FIXEDDELAY: Supported in ECP3, MachXO2, and XP2 devices. 2). DELAYC: Supported in ECP3 devices. 3). DELAYB: ...
2453 - LatticeXP2: What does the I/O Type in Table 14-1 of TN1141 mean? For example, is the INITN pin only used as a bi-directional pin when CFG0 is high?
The I/O Type in Table 14-1 of TN1141 is for all the sysCONFIG pins during configuration. For the dual-purpose sysCONFIG pins, when they are used as general purpose I/Os after configuration, they can use any I/O type such as input, output and ...
6442 - MIPI for Nexus FPGAs: Does it allowed to assign MIPI signals (clock + data) across multiple different DQS group and implementing multiple MIPI signals (clock + data) in one DQS group?
Yes the user can assign MIPI signals across different DQS groups. The current RD for CertusPro-NX implements the same idea. Example#1 - MIPI signals across multiple DQS groups: MIPI DSI-CSI2-OpenLDI-LVDS-Int_Bridge rx_clk_p_i MIPI_DPHY BDQ114 ...