5645 - MachXO2/MachXO3 :Are there any power supply sequence requirement for MachXO2 and MachXO3 devices?
POR is controlled by VCC and VCCIO0. As such, these banks should be brought up first. The typical I/O behavior during power-up is described below:
The internal power-on-reset (POR) signal is deactivated when VCC and VCCIO0 reach VPORUP level. This is defined in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of the MachXO2 data sheet. After the POR signal is deactivated, the FPGA core logic becomes active.
Ensure that all VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. The default configuration of the I/O pins in a blank device is tri-state with a weak pull-down to GND. Some pins such as PROGRAMN and the JTAG pins have weak pull-up to VCCIO as the default functionality. The I/O pins maintain the blank configuration until VCC and VCCIO (for I/O banks containing configuration I/Os) reach VPORUP levels. At this time, the I/Os take on the user-configured settings only after a proper download/configuration.
Basically, the device does not start configuration until VCC and VCCIO0 are both powered to Vporup. Because of this, you ideally want your clocks and resets in Bank 0 with this device.
Lastly, please sure that you are applying the right VCC voltage depending on what specific part number you are using. MachXO2 ZE/HE (1.2 V) / MachXO2 HC (2.5 V / 3.3 V) / MachXO3L/LF E (1.2 V) MachXO3L/LF C (2.5 V/3.3 V).
Note: If you are doing external boot or dual boot, you need to bring up VCCIO2 first (or at least at the same time as VCCIO0 and VCC) since SPI is on bank 2.