Current-Mode Logic (CML) input and output buffers must be terminated for proper operation. CML uses true double termination. Rather than LVDS which is only terminated at the receiver. This means that any signal reflection back to the source reflects back to the receiver with little attenuation. This limits the data rate and trace length that LVDS can drive whereas CML provides longer reach and achieves higher data rates.

The Lattice devices provide separate Rx and Tx termination power nodes for each SERDES channel, allowing the receiver input termination and transmitter output termination to be biased at user defined levels independent of the core SERDES voltage (1.2V). The input and output supplies are respectively VCC(VDD)IB and VCC(VDD)OB.

Typical CML I/O uses internal 50-ohm pull up resistors for termination. This is required to pullup a "1" level since CML only drives "0" levels. They must be terminated to voltage supplies between 1.2V and 1.5V to ensure proper operation. The sole purpose of these terminations are to match the line between drivers and receivers. A mismatch in these terminations will cause potential current draws on the device pins and create undesirable jitter however raising or lowering these supplies will not influence voltage swings. In cases where a particular SERDES channel is not used the associated VCC(VDD)IB and VCC(VDD)OB supply pins can be left unconnected.