538 - LatticeECP2/M / LatticeECP3 / LatticeSC/M: What is the recommended connection for the XRES pin for the LatticeECP2/M, LatticeECP3, and LatticeSC/M devices?

538 - LatticeECP2/M / LatticeECP3 / LatticeSC/M: What is the recommended connection for the XRES pin for the LatticeECP2/M, LatticeECP3, and LatticeSC/M devices?

LatticeECP2/M, LatticeECP3, and LatticeSC/M devices require a single external resistor which is used to create the bias currents for the IO. This resistor is connected between the XRES pin and ground. The device will not initialize and configuration will not complete if this resistor is missing. Also, there is no boundary scan register on the external resistor pad.

The XRES pin is a single dedicated pin per device. It is NOT associated with any particular sysIO bank. This pin MUST have an external 10K-ohm +/-1% pull-down resistor to PCB ground.

The LatticeSC/M devices have a simlar XRES pin however is requires a 1K-ohm +/- 1% pull-down resistor. Different from LatticeECP2/M and LatticeECP3, the device will initialize without this connection. However the device will not operate correctly if this pull-down is not connected.

This resistor is used for a calibration reference for sensitive on-chip circuitry. It must be carefully placed on the PCB layout to reduce any likelihood of coupled noise influencing the circuit. Use the following PCB recommendations.

  • The resistor connection must be kept very close to the FPGA device pin minimizing any long traces to the resistor.
  • The ground connection must be kept very short.
  • Do not add any other components such as decoupling capacitors as this can interfere with the proper operation of the circuit.