Description: 

Hysteresis is implemented by separating the rising and falling edge threshold trip points.

GPIO with no hysteresis has a common decision point on rising and falling edges
- The decision point is between VIL(max) and VIH(min) depending on PVT

GPIO with hysteresis will add separation between rising decision point and falling decision point.
- These 2 points will still to be within VIL(max) and VIH(min).
- Note, hysteresis does not change VIL/VIH specification. 

For example, for MachXO2/3 LVCMOS33 (other families are similar):
- The decision threshold could be 1.40v.
    - This will move around with PVT, but will always be between 0.8v VIL(max) and 2.0v VIH(min), with margin.
- For a hysteresis setting of 250mv
    - The thresholds change to 1.525v (rising) and 1.275v (falling) typical
        - 1.525 - 1.275 = 250mV typical
- Likewise, for a hysteresis setting of 450mv
    - The thresholds change to 1.625v (rising) and 1.175v (falling) typical
        - 1.625 - 1.175 = 450mV typical
Note: the hysteresis thresholds are always within VIL(max) and VIH(min) with sufficient margin for PVT.