5268 - In CrossLink, Can the hard-dphy pins be used as GPIO instead of dphy?
No, Hard-DPHY IOs in Crosslink are dedicated pins, cannot be used as GPIO.
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5951 - iCE40UP: If an external clock/oscillator is going to be used, what pins should be used if the intention is to utilize the primary clock routing?
Description: GBIN (Global Buffer Input) pins represent the best pin to drive a global buffer from an external source. Solution: For example, in an iCE40 Ultraplus SG48 package, the pins that can be used are Pin20, Pin35, Pin37, and Pin44. After ...
7312 - Crosslink: How to implement OPENDRAIN on Bi-Directional I/O port in CrossLink device?
CrossLink I/O does not have OPENDRAIN support for bi-directional pins. This feature is limited by the device hardware itself. However, this product still offers OPENDRAIN support but only limited to output ports only.
5983 - Platform Manager 2: How many external DC-DC can be connected with GPIO output?
Controlling various DC-DC enable pins using a single GPIO will be dependent on the internal pull up within the DC-DC. Any number of DC-DC is may be enabled as long as the maximum GPIO source current does not exceed. The other tricky part will be ...
7055 - All Nexus: What pins are preferred for output clocks?
For input clocks, we can only used dedicated clock pins, PCLK or GPLL input pins for PLL reference clock. For output clocks, any IO pin can be used. There is no restriction for this.
6844 - CrossLink-NX ECLK: How can I fit 10 ECLKs on one FPGA?
For each bank, only 4 ECLKs (4 sets of PCLK pins) are available. You may be using more than 4 ECLKs per bank. Carefully, distribute and assign ECLKs to banks 3, 4, and 5 to avoid this issue. You can do this by simply assigning the clock lanes of each ...