4247 - MachXO2: Do the JTAG pins support hysteresis when JTAG_PORT is set to ENABLE?

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• 725 - Does the MachXO device family support true LVDS buffers?<br>

  The larger two devices (LCMXO1200 & LCMXO2280) in the MachXO family support True LVDS I/O. To set up "true LVDS" on the input side, connect a 100 ohm terminating resistor across the 'true' and 'compliment' input terminals. On the output side, no ...

• 7211 - Why is PULLMODE set to NONE when port is configured as output?

  Description: There is no PULLMODE for output-only ports, therefore all output pins PULLMODE will be fixed to 'NONE' in the tool. For bi-directional pins, PULLMODE will be relevant, and thus it will be set to 'NONE' when the bi-directional pin acts as ...

• 619 - What is the detailed power-up sequence for a MachXO device?

  The following is the power-up sequence for a MachXO device: - All IOs trisate with a weak pull up - POR (Power On Reset) for internal circuitry asserted - Vcc and Vccaux reach minimum recommended datasheet levels - POR (Power On Reset) for internal ...

• 246 - MachXO: How is the TSALL pin used in the MachXO?

  Solution: TSALL is a programmable IO which can be used to Tristate all IOs when asserted. To use TSALL in your design, instantiate the TSALL component as shown below: TSALL Verilog HDL Example (MachXO) TSALL   TSALL_INST (.TSALL ()); TSALL VHDL ...

• 6738 - All Nexus: What is the function of the PCLKDIVTESTINPX pins of the PCLKDIV primitive and what values should these pins be driven?

  The PCLKDIVTESTINPX pins, together with the TESTEN_PCLKDIV and TESTMODE_PCLKDIV on the parameter lists, are signals and parameters used for test modes to test the PCLKDIV primitive in the factory. To enable normal operation, you need to set the ...