4247 - MachXO2: Do the JTAG pins support hysteresis when JTAG_PORT is set to ENABLE?

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• 725 - Does the MachXO device family support true LVDS buffers?

  The larger two devices (LCMXO1200 & LCMXO2280) in the MachXO family support True LVDS I/O. To set up "true LVDS" on the input side, connect a 100 ohm terminating resistor across the 'true' and 'compliment' input terminals. On the output side, no ...

• Lattice Diamond: How do i make sure that Write Enable and Chip Enable for my EBR to be inactive to avoid EBR contents glitch and corruption?

  Description: Users may encounter an INFO message shown below if there design has an EBR and GSR is disabled. chipcheck: INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make ...

• 7211 - Why is PULLMODE set to NONE when port is configured as output?

  Description: There is no PULLMODE for output-only ports, therefore all output pins PULLMODE will be fixed to 'NONE' in the tool. For bi-directional pins, PULLMODE will be relevant, and thus it will be set to 'NONE' when the bi-directional pin acts as ...

• 619 - What is the detailed power-up sequence for a MachXO device?

  The following is the power-up sequence for a MachXO device: - All IOs trisate with a weak pull up - POR (Power On Reset) for internal circuitry asserted - Vcc and Vccaux reach minimum recommended datasheet levels - POR (Power On Reset) for internal ...

• 6738 - All Nexus: What is the function of the PCLKDIVTESTINPX pins of the PCLKDIV primitive and what values should these pins be driven?

  The PCLKDIVTESTINPX pins, together with the TESTEN_PCLKDIV and TESTMODE_PCLKDIV on the parameter lists, are signals and parameters used for test modes to test the PCLKDIV primitive in the factory. To enable normal operation, you need to set the ...