Timing Closure Inquiry / Failure
7480 - Lattice Radiant: Why are there missing timing paths analyzed on R3.0 when it was compared with R3.1 and later?
Description: When users try to compare timing analysis paths from R3.1 and later with R3.0, there are timing violations/timing paths found in R3.1 and later that cannot be found in R3.0. Solution: This is a known issue on Software version R3.0 The ...
7459 - Radiant: How do -start and -end work for -hold on multicycle constraints?
For a multicycle constraint, -start and -end indicate to which clock (launch or capture clock) the constraint is referenced. Below is an example: Setting up the Example: Let's say we have a path from register coutr1_reg[5] to register coutr2_0io[4]. ...
1150 - Diamond: What does the M or Minimum Speed grade mean in a Lattice I/O timing report?
The M or Minimum Speed grade device appears to be faster than the fastest speed grade in the I/O timing report and the term "Minimum Speed grade" can be a bit confusing. For starters, it does NOT mean the slowest silicon device. The term refers to ...
2292 - Diamond: Why is there a Timing Rule Check violation in the trace report on a ODDRX4B element for timing between the SCLK & ECLK inside this element?
This violation should not occur if the module is generated using IPExpress. If you are generating the module using IPExpress and continue to get this timing violation, check your preference file to make sure there is a FREQUENCY preference assigned ...
941 - Diamond: Timing: Why does the hold analysis use a different speed grade?
Diamond: Timing: When running a Hold analysis the default speed grade run is the -M. The -M speed grade is the fastest device across a process and is usually the worst case for a hold analysis. Ideally when looking at a hold analysis the IO Timing ...
6598 - Diamond: How do we solve timing violations from Dual Clock FIFOs or other memory modules?
Solution: You can do the following: 1. Make sure that the user have enabled the Output Register option on the IP GUI. Setting this should decrease the C2Q delay as this provides a pipeline to the critical path. 2. If the failing path's delay ratio is ...
940 - Diamond: Timing: Why are there two trace reports in the Lattice software?
Diamond: Timing: There are two trace reports (a Map trace report and a Place-and-Route (PAR) trace report) that serve two different purposes. The Map Trace report has estimated routing. It should be used to verify the paths you expect are being ...
939 - Lattice Diamond: How can I block clock transfers in the timing analysis tool?
A clock domain transfer or crossing occurs when one register in a data path is clocked by CLKA and one register by CLKB. To block this transfer from the timing analysis use the preference: BLOCK INTERCLOCKDOMAIN If you are looking to relax or analyze ...
938 - Timing: What is the I/O Timing Report?
Timing: The I/O Timing Report is a used to analyze the the IO timing in your design (Tsu, Th, Tco). The IO Timing Report sweeps across all the speed grades to determine the worst case.
2084 - Diamond: How to check the un-constrained connections in Lattice Diamond?
In Lattice Diamond, when user set up the strategies for either "MAP TRACE" or "Place & Route TRACE", select "Check unconstrained Path" to "True". TRACE will list out all the connections that are not covered by preferences. To make better use of this ...
931 - Diamond: Timing: How do I define the skew of a registered bus to IOs?
Diamond: Timing: The preference to use is CLOCK_TO_OUT with the Max and Min options. Max is used by the setup analysis Min is used by the Hold analysis. For example: CLOCK_TO_OUT "dout_*" MAX 4 ns MIN 3 ns CLKNET "clk_2x" ; Where the * denotes the ...
1993 - Diamond: Why does the place and route tool not fix hold violation for the design despite Auto Hold-Time Correction being set to "On"?
The tool disables Hold-Time Correction due to the following reasons: 1. If there is a setup timing error, auto hold-time correction will not be done. If user wants the correction to be done anyway, add the following option to “Command Line Options” ...
1964 - Diamond: How can users disable irrelevant clock domain crossings during the device implementation?
Timing paths that contain clock domain crossings are paths between two registers that are clocked with two clocks. After performing timing analysis using Place and Route TRACE, such timing paths usually have the following source and destination ...
740 - Lattice ispLEVER: Timing Analysis: What is the I/O Timing Report?
Lattice ispLEVER: Timing Analysis: The I/O Timing Report (.ior) is a used to report the IO timing analysis of your design. Input Setup and Hold times (Tsu, Th) and Clock-to-Output times (Tco) are reported. The IO Timing Report sweeps across all the ...
711 - Lattice ispVM system: What are the constraint files used by ispLEVER Classic?
The ispLEVER Classic software employs three types of constraint files: Lattice constraint input file (.lci), Lattice constraint temporary file (.lct), and Lattice constraint output file (.lco). The .lci file consists of two types: the parent .lci ...
692 - Lattice Diamond: Does the Lattice timing analysis tool only analyze 4096 timing paths at maximum?
The timing analysis tool does analyze all timing paths in your design. For timing closure, the analyzer will address all failing timing paths even if they exceed 4096 paths. It is for MAP and Place & Route TRACE reporting purpose only that up to 4096 ...
3360 - Diamond / Timing Closure: Does the clock to out timing analysis calculate relative skew between the forwarded clock output and the data output in a source synchronous transmit interface?
Solution: In the scenario where both the forwarded clock and data use the same clock source, the trace's clock_to_out preference analyzes the data and forwarded output clock paths with respect to the input clock(clocking the ODDR). The IO Timing ...
1713 - Diamond: When using the FREQUENCY preference, when would I want to use the HOLD_MARGIN keyword?
The HOLD_MARGIN preference is used to indicate the extra hold margins user can apply to the frequency preferences. If HOLD_MARGIN is not specified The 'min' path is optimized using the default timing numbers for each components, this could result in ...
610 - Lattice IspLever: What does a warning about 'potential circuit loops' mean and how can I find them?
Description: When doing a 'map timing checkpoint' in ispLEVER, you might see the following message: "1 potential circuit loop found in timing analysis" Solution: This message is related to conditions being met to latch in data where "potential" ...
1712 - Diamond: How can user get estimated timing of my design before running place and route?
In both ispLEVER and Lattice Diamond tools, user can generate the timing using the static timing analysis tool after map, and before place and route. The static timing analyzer (TRCE) will generate timing using estimated models, as well as the fanout ...
1591 - Diamond / LatticeECP3: What is the guideline to use a general routing based clock for the LatticeECP3 device?
For the LatticeECP3 device, general routing can be used route as the clock resource rather than using dedicated clock resources. This should only be considered for non-critical clock paths and for small areas of the design. Clocks routed using the ...
1587 - Diamond: What are the different factors that affect device speed, temperature and voltage selection during software timing analysis?
Software uses different temperatures and voltages for timing analysis based on the following factors: Commercial vs. Industrial Part selection.: Commercial part selection enforces the following DEFAULT temperatures for Setup and Hold analysis (based ...
2724 - Lattice Diamond: Where can I see the results of changes made in the Input Delay block?
The Place and Route TRACE report will only show the delays through the Input Data DELAY block if the delay values are static. The changes can be seen in the parameters under the INPUT_SETUP preference section of the TRACE report.
336 - Lattice Diamond: Why does my static timing score not improve after adding place and route iterations?
Fundamentally, the static time score will depend on the router's perfomance, which will vary from design to design. Typically for a small design, a timing score will reach a certain level after a few iterations and adding more iterations might not ...
5819 - Diamond: Why did TRACE not detect a violation in the LSR pin, but during simulation, it was detected?
The static timing engine does static timing analysis only. The LSR pin is not a clock pin and the pulse width requirement on this pin must be guaranteed by the designer. The static timing engine does not check for the pulse width on the LSR pin. ...
5796 - MachXO2, MachXO3: What is the value of tSUD_PFU and tHD_PFU in the XO2/XO3 series?
Starting from the XO2 device, many of the timing parameters were removed to simplify the datasheets, as there were too many speed-grade and package data to list. To simplify, the value for this kind of parameter can be obtained from the trace report. ...
261 - Lattice Diamond: Why is the maximum frequency Fmax in the Place and Route Trace report different from that in the Performance Analyst(PA) report?
The Trace report determines the Fmax of a design taking into account all of the timing constraints in the projects preference file (i.e.*.lpf). For example, the preference file may have a multicycle constraint: MULTICYCLE FROM GROUP "START_WORD_REG" ...
231 - ispLEVER: Why are the registers of the design being clocked at a faster rate than intended?
Simulation and hardware show that registers are clocked with a fast clock in the design, while they are supposed to be clocked by a slow clock. This usually happens when the slow clock used for the registers is generated from a fast clock. The ...
212 - Diamond: Why do users have preference items in the trace report with 0 timing score?
There are several reasons why users will see this happen: The timing constraint specified is covered by another timing constraint in the preference file. This is most often seen when the design has two related clocks. Trace will provide timing ...
200 - Diamond: How do user get a reasonable I/O timing report when PLL phase shift is very large?
When user change the PLL phase to improve the Tco, user caan program the PLL phase delay by more than 180 degree, e.g. 315 degree. Its equivalent effect is to advance 45 degree if one clock cycle latency is acceptable. But the Lattice software will ...
198 - Diamond: How do users improve the performance of FPGA designs that use Embedded Block RAM (EBR)?
Many times FPGA designs that contain Embedded Block RAM (EBR) do not meet system performance requirements. Here are some suggestions for improving the performance of designs using EBR. There may be a large amount of logic surrounding the EBR. Inspect ...
1237 - Lattice ispLEVER: ispLEVER issued warning for a design with EBR in ASYNC Reset mode
Lattice ispLEVER: This is due to a hardware restriction and there is a possibility that you may destroy the memory content if this operation isn't performed properly. This is documented in LatticeECP2/M Family Data Sheet (DS1006.pdf, Page 2-20) and ...
134 - Diamond: How can user block clock domain transfers where there is already synchronizer circuits in place?
The Lattice Static Timing Analyzer Trace analyzes all clock domain transfers in which it can relate the source and destination clock domains. This may not always be desired. User may utilize their own synchronizer to handle the transfer between the ...
132 - Lattice Diamond: Where can I find information on the clock domains in my design?
The Place and Route TRACE report contains a seciton titled "Clock Domains Analysis" which provides information on every clock domain in the design. This includes the clock net name, source, number of loads, and which clock domains transfer data into ...
129 - Lattice Diamond: How can I single out a specific path or transfer in the timing analysis TRACE report?
TRACE lists the paths per timing preference starting from the worst case path going down. Let's say you want to look at a path that maybe the 1001st worst case path in the design. You do not want to list 1001 paths in the trace report. How can this ...
6926 - Lattice Diamond: When do I encounter MWP timing error occur (At >Fmax) when constraining Edge Clock?
Minimum pulse width timing error is triggered if and only if the minimum pulse width pin is connected to the clock net. If the pin is not connected to a clock net, then it does not affect the frequency requirement on that clock net.
7279 - Lattice Diamond: Does the MAXDELAY preference/constraint, and its option MIN, affect PAR? Or is it only used to check against TRACE timing?
Based on the MAXDELAY preference documentation found in Lattice Diamond Help, we see that MAXDELAY preference is only checked with TRACE timing analysis, but it is not factored in with PAR. Thus, PAR is unaffected by any MAXDELAY preference including ...
7278 - What are some ways a user can do to optimize RTL and reduce the equivalent logic levels in PAR?
Large logic levels can be due to long combinational logic with complex conditional/comparison operations such as the example below: else if((param_trigger_mode == 1'b1) && param_trigger_enable && (param_trigger_channel == 0) && ...
Radiant: How does the user interpret the Single Clock Domain table entries on the Clock Summary section of the Place & Route Timing Analysis Report?
The Single Clock Domain table of the Clock Summary Section of the Place & Route Timing Analysis report: There are three values on this table: 1. The Target is the frequency or period based on the clock constraint. This should always be the lowest of ...
6905 - Lattice Diamond: Is the Performance/Timing/Delay data for MACHXO3 shown in External Switching Characteristics Table covered for all temperature range?
HW Performance/Timing/Delay for Both Commercial and Industrial are the same only up until 85C. So in Diamond, it is expected that we see that changing the operating temperature above this temperature We can see a change in Performance in Timing ...
Next page