2724 - Lattice Diamond: Where can I see the results of changes made in the Input Delay block?<br><br>

• Related Articles

• 1046 - Lattice Diamond: What is the "BLOCK INTERCLOCKDOMAIN PATH" preference used for? <br>

  Lattice Diamond: This constraint is used to block paths that involve data transfer between registers that are clocked by different clock nets. If used without understanding, it will block all clocks domains from each other, even if they are supposed ...

• Lattice Diamond: How do we tell the software to reduce the DSP block utilization and use LUTs instead?

  Lattice Synthesis Engine (LSE) has the ability to reduce the total DSP block utilization using these steps: Go to Project > Active Implementation > Select Synthesis Tool Select "Lattice LSE" and click OK. Go to Project > Active Strategy > LSE ...

• 5727 - Programmer: Does the customer-made FT2232H-based programmer supported by the Lattice Diamond Programmer software?

  Lattice is using FTDI chip or FT2232H, therefore technically, the Lattice Diamond Programmer should recognize the available customer-made FT2232H based-hardware. By using Lattice Diamond Programmer Software, you can read and program the device the ...

• 198 - Diamond: How do users improve the performance of FPGA designs that use Embedded Block RAM (EBR)?

  Many times FPGA designs that contain Embedded Block RAM (EBR) do not meet system performance requirements. Here are some suggestions for improving the performance of designs using EBR. There may be a large amount of logic surrounding the EBR. Inspect ...

• 939 - Lattice Diamond: How can I block clock transfers in the timing analysis tool? <br>

  A clock domain transfer or crossing occurs when one register in a data path is clocked by CLKA and one register by CLKB. To block this transfer from the timing analysis use the preference: BLOCK INTERCLOCKDOMAIN If you are looking to relax or analyze ...