7278 - What are some ways a user can do to optimize RTL and reduce the equivalent logic levels in PAR?

Large logic levels can be due to long combinational logic with complex conditional/comparison operations such as the example below:

else if((param_trigger_mode == 1'b1) && param_trigger_enable && (param_trigger_channel == 0) && lf_start_sample_enable)

begin

if(lf_data_out[31] && ((32'hffffffff - lf_data_out[31:0]) >= param_trigger_threshold))

User can modify these types of RTL code by doing the following:

1. Some pre-computation and adding pipeline stages in between these calculations to break down the combinational chain

2. Reducing as many logical operations/calculations (i.e. if-else statements, comparison operation) as possible

3. Duplicate and isolate the signals so that they become independent of each other

As a consequence of doing the steps abovementioned, there will be some effect on the functionality/latency of the modified transfer. Thus, it is recommended that the user always verify the design's logic through simulation.

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7278 - What are some ways a user can do to optimize RTL and reduce the equivalent logic levels in PAR?

7278 - What are some ways a user can do to optimize RTL and reduce the equivalent logic levels in PAR?

Related Articles

6706 - Diamond 3.12: Is it normal for the placement and routing, and in turn, the generated bitstream, to change when a part of the RTL is changed, even if it wouldn't change the overall logic?

1907 - Diamond: Can user run multiple Place and Route (PAR) in parallel?

6659 - Diamond 3.12 and All FPGA: Is it normal for the placement and routing, and in turn, the generated bitstream, to change when a part of the RTL is changed, even if it wouldn't change the overall logic?

7081 - Radiant: How can user perform Timing Analysis using a different speed grade other than the speed grade of the selected device (or the PAR speed grade)?

6142 - Lattice Diamond: Why LSE and Synplify Pro has different RTL View implementation?