6659 - Diamond 3.12 and All FPGA: Is it normal for the placement and routing, and in turn, the generated bitstream, to change when a part of the RTL is changed, even if it wouldn't change the overall logic?

6659 - Diamond 3.12 and All FPGA: Is it normal for the placement and routing, and in turn, the generated bitstream, to change when a part of the RTL is changed, even if it wouldn't change the overall logic?

Description:
Diamond software just checks ANY changes in the RTL for it to change its seed.

Solution: 
Yes. The software generates a new PAR seed every time a change is made to the design RTL, regardless of the change's impact on the overall logic of the design.